80C186EC/188EC, 80L186EC/188EC
INSTRUCTION SET SUMMARY (Continued)
80C186EC 80C188EC
Function
Format
Comments
Clock
Clock
Cycles
Cycles
LOGIC (Continued)
e
XOR
Exclusive or:
Reg/memory and register to either
Immediate to register/memory
Immediate to accumulator
0 0 1 1 0 0 d w
1 0 0 0 0 0 0 w
0 0 1 1 0 1 0 w
1 1 1 1 0 1 1 w
mod reg r/m
mod 1 1 0 r/m
data
3/10
4/16
3/4
3/10*
4/16*
3/4
e
1
data
data if w
e
data if w
1
8/16-bit
e
NOT
Invert register/memory
mod 0 1 0 r/m
3/10
3/10*
STRING MANIPULATION
e
e
e
e
e
MOVS
CMPS
SCAS
LODS
STOS
Move byte/word
1 0 1 0 0 1 0 w
1 0 1 0 0 1 1 w
1 0 1 0 1 1 1 w
1 0 1 0 1 1 0 w
1 0 1 0 1 0 1 w
0 1 1 0 1 1 0 w
0 1 1 0 1 1 1 w
14
22
15
12
10
14
14
14*
22*
15*
12*
10*
14
Compare byte/word
Scan byte/word
Load byte/wd to AL/AX
Store byte/wd from AL/AX
e
INS
Input byte/wd from DX port
e
OUTS
Output byte/wd to DX port
14
Repeated by count in CX (REP/REPE/REPZ/REPNE/REPNZ)
e
e
e
e
e
a
a
8 8n*
MOVS
CMPS
SCAS
LODS
STOS
Move string
Compare string
Scan string
Load string
1 1 1 1 0 0 1 0
1 1 1 1 0 0 1 z
1 1 1 1 0 0 1 z
1 1 1 1 0 0 1 0
1 1 1 1 0 0 1 0
1 1 1 1 0 0 1 0
1 0 1 0 0 1 0 w
1 0 1 0 0 1 1 w
1 0 1 0 1 1 1 w
1 0 1 0 1 1 0 w
1 0 1 0 1 0 1 w
0 1 1 0 1 1 0 w
8
8n
a
a
5
5
6
22n
15n
11n
5
5
6
22n*
15n*
11n*
a
a
a
a
a
a
Store string
6
9n
8n
6
9n*
8n*
e
a
a
a
a
INS
Input string
8
8
8
8
e
OUTS
Output string
1 1 1 1 0 0 1 0
0 1 1 0 1 1 1 w
8n
8n*
CONTROL TRANSFER
e
CALL
Call:
Direct within segment
1 1 1 0 1 0 0 0
1 1 1 1 1 1 1 1
disp-low
disp-high
15
19
Register/memory
mod 0 1 0 r/m
13/19
17/27
indirect within segment
Direct intersegment
1 0 0 1 1 0 1 0
1 1 1 1 1 1 1 1
segment offset
segment selector
23
31
i
(mod 11)
Indirect intersegment
mod 0 1 1 r/m
38
54
e
JMP
Unconditional jump:
Short/long
1 1 1 0 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 1 1 1
disp-low
disp-low
14
14
14
14
Direct within segment
disp-high
Register/memory
mod 1 0 0 r/m
11/17
11/21
indirect within segment
Direct intersegment
Indirect intersegment
1 1 1 0 1 0 1 0
segment offset
segment selector
14
26
14
34
i
(mod 11)
1 1 1 1 1 1 1 1
mod 1 0 1 r/m
Shaded areas indicate instructions not available in 8086/8088 microsystems.
NOTE:
*Clock cycles shown for byte transfers, for word operations, add 4 clock cycles for all memory transfers.
54
INTEL [ INTEL ]
