80C186EC/188EC, 80L186EC/188EC
INSTRUCTION SET SUMMARY (Continued)
80C186EC 80C188EC
Function
Format
Comments
Clock
Clock
Cycles
Cycles
DATA TRANSFER (Continued)
e
SEGMENT
Segment Override:
CS
0 0 1 0 1 1 1 0
0 0 1 1 0 1 1 0
0 0 1 1 1 1 1 0
0 0 1 0 0 1 1 0
2
2
2
2
2
2
2
2
SS
DS
ES
ARITHMETIC
e
ADD
Add:
Reg/memory with register to either
Immediate to register/memory
Immediate to accumulator
0 0 0 0 0 0 d w
1 0 0 0 0 0 s w
0 0 0 0 0 1 0 w
mod reg r/m
mod 0 0 0 r/m
data
3/10
4/16
3/4
3/10*
4/16*
3/4
e
data if s w 01
data
e
e
data if w
1
1
8/16-bit
8/16-bit
e
ADC
Add with carry:
Reg/memory with register to either
Immediate to register/memory
Immediate to accumulator
0 0 0 1 0 0 d w
1 0 0 0 0 0 s w
0 0 0 1 0 1 0 w
mod reg r/m
mod 0 1 0 r/m
data
3/10
4/16
3/4
3/10*
4/16*
3/4
e
data if s w 01
data
data if w
e
INC
Increment:
Register/memory
Register
1 1 1 1 1 1 1 w
0 1 0 0 0 reg
mod 0 0 0 r/m
3/15
3
3/15*
3
e
SUB
Subtract:
Reg/memory and register to either
Immediate from register/memory
Immediate from accumulator
0 0 1 0 1 0 d w
1 0 0 0 0 0 s w
0 0 1 0 1 1 0 w
mod reg r/m
mod 1 0 1 r/m
data
3/10
4/16
3/4
3/10*
4/16*
3/4*
e
data if s w 01
data
e
e
data if w
1
1
8/16-bit
8/16-bit
e
SBB
Subtract with borrow:
Reg/memory and register to either
Immediate from register/memory
Immediate from accumulator
0 0 0 1 1 0 d w
1 0 0 0 0 0 s w
0 0 0 1 1 1 0 w
mod reg r/m
mod 0 1 1 r/m
data
3/10
4/16
3/4
3/10*
4/16*
3/4*
e
data if s w 01
data
data if w
e
DEC
Decrement
Register/memory
Register
1 1 1 1 1 1 1 w
0 1 0 0 1 reg
mod 0 0 1 r/m
3/15
3
3/15*
3
e
CMP
Compare:
Register/memory with register
Register with register/memory
Immediate with register/memory
Immediate with accumulator
0 0 1 1 1 0 1 w
0 0 1 1 1 0 0 w
1 0 0 0 0 0 s w
0 0 1 1 1 1 0 w
1 1 1 1 0 1 1 w
0 0 1 1 0 1 1 1
0 0 1 0 0 1 1 1
0 0 1 1 1 1 1 1
0 0 1 0 1 1 1 1
mod reg r/m
mod reg r/m
mod 1 1 1 r/m
data
3/10
3/10
3/10
3/4
3/10
8
3/10*
3/10*
3/10*
3/4
3/10*
8
e
data if s w 01
data
e
data if w
1
8/16-bit
e
e
e
e
e
NEG
AAA
DAA
AAS
DAS
Change sign register/memory
ASCII adjust for add
mod 0 1 1 r/m
Decimal adjust for add
4
4
ASCII adjust for subtract
Decimal adjust for subtract
7
7
4
4
e
MUL
Multiply (unsigned):
1 1 1 1 0 1 1 w
mod 100 r/m
Register-Byte
Register-Word
Memory-Byte
Memory-Word
26–28
35–37
32–34
41–43
26–28
35–37
32–34
41–43*
Shaded areas indicate instructions not available in 8086/8088 microsystems.
NOTE:
*Clock cycles shown for byte transfers, for word operations, add 4 clock cycles for all memory transfers.
52
INTEL [ INTEL ]
