80C186EC/188EC, 80L186EC/188EC
INSTRUCTION SET SUMMARY (Continued)
80C186EC
Clock
80C188EC
Clock
Function
Format
Comments
Cycles
Cycles
ARITHMETIC (Continued)
e
IMUL
Integer multiply (signed):
1 1 1 1 0 1 1 w
mod 1 0 1 r/m
Register-Byte
Register-Word
Memory-Byte
Memory-Word
25–28
34–37
31–34
40–43
25–28
34–37
32–34
40–43*
e
(signed)
e
0
IMUL
Integer Immediate multiply
0 1 1 0 1 0 s 1
1 1 1 1 0 1 1 w
mod reg r/m
data
data if s
22–25/
29–32
22–25/
29–32
e
DIV
Divide (unsigned):
mod 1 1 0 r/m
Register-Byte
Register-Word
Memory-Byte
Memory-Word
29
38
35
44
29
38
35
44*
e
IDIV
Integer divide (signed):
1 1 1 1 0 1 1 w
mod 1 1 1 r/m
Register-Byte
Register-Word
Memory-Byte
Memory-Word
44–52
53–61
50–58
59–67
44–52
53–61
50–58
59–67*
e
e
e
e
AAM
AAD
CBW
CWD
ASCII adjust for multiply
ASCII adjust for divide
Convert byte to word
1 1 0 1 0 1 0 0
1 1 0 1 0 1 0 1
1 0 0 1 1 0 0 0
1 0 0 1 1 0 0 1
0 0 0 0 1 0 1 0
0 0 0 0 1 0 1 0
19
15
2
19
15
2
Convert word to double word
4
4
LOGIC
Shift/Rotate Instructions:
Register/Memory by 1
1 1 0 1 0 0 0 w
1 1 0 1 0 0 1 w
1 1 0 0 0 0 0 w
mod TTT r/m
mod TTT r/m
2/15
2/15
a
a
a
a
Register/Memory by CL
5
n/17
n/17
n
5
n/17
n/17
n
a
a
a
a
Register/Memory by Count
mod TTT r/m
count
5
n
5
n
TTT Instruction
0 0 0
0 0 1
0 1 0
0 1 1
ROL
ROR
RCL
RCR
1 0 0 SHL/SAL
1 0 1
1 1 1
SHR
SAR
e
AND
And:
Reg/memory and register to either
Immediate to register/memory
Immediate to accumulator
0 0 1 0 0 0 d w
1 0 0 0 0 0 0 w
0 0 1 0 0 1 0 w
mod reg r/m
mod 1 0 0 r/m
data
3/10
4/16
3/4
3/10*
4/16*
3/4*
e
e
e
data
data if w
data if w
data if w
1
1
1
e
data if w
1
1
1
8/16-bit
8/16-bit
8/16-bit
e
TEST And function to flags, no result:
Register/memory and register
1 0 0 0 0 1 0 w
1 1 1 1 0 1 1 w
1 0 1 0 1 0 0 w
mod reg r/m
mod 0 0 0 r/m
data
3/10
4/10
3/4
3/10
4/10*
3/4
Immediate data and register/memory
Immediate data and accumulator
data
e
e
data if w
e
OR Or:
Reg/memory and register to either
Immediate to register/memory
Immediate to accumulator
0 0 0 0 1 0 d w
1 0 0 0 0 0 0 w
0 0 0 0 1 1 0 w
mod reg r/m
mod 0 0 1 r/m
data
3/10
4/16
3/4
3/10*
4/16*
3/4*
data
data if w
Shaded areas indicate instructions not available in 8086/8088 microsystems.
NOTE:
*Clock cycles shown for byte transfers, for word operations, add 4 clock cycles for all memory transfers.
53
INTEL [ INTEL ]
