80960JD
CLKIN
PLL, Clocks,
Power Mgmt
4 KByte Instruction Cache
Two-Way Set Associative
32-bit buses
address / data
Physical Region
Configuration
Bus
Control Unit
Bus Request
Queues
Control
21
Address/
Data Bus
32
TAP
5
Boundary Scan
Controller
Instruction Sequencer
Constants
Control
Two 32-Bit
Timers
Interrupt
Port
9
8-Set
Local Register Cache
Multiply
Divide
Unit
Execution
and
Address
Generation
Unit
effective
address
SRC1
SRC2
SRC1
SRC2
DEST
DEST
Programmable
Interrupt Controller
Memory
Interface
Unit
Memory-Mapped
Register Interface
128
Global / Local
Register File
SRC1
SRC2 DEST
32-bit Address
32-bit Data
SRC1
DEST
1 Kbyte
Data RAM
2 Kbyte Direct
Mapped Data
Cache
3 Independent 32-Bit SRC1, SRC2, and DEST Buses
Figure 2. 80960JD Block Diagram
2.1
80960 Processor Core
• 128-bit register bus speeds local register caching
• 4 Kbyte two-way set associative, integrated
instruction cache
• 2 Kbyte direct-mapped, integrated data cache
• 1 Kbyte integrated data RAM delivers zero wait
state program data
The 80960Jx family is a scalar implementation of the
80960 Core Architecture. Intel designed this
processor core as a very high performance device
that is also cost-effective. Factors that contribute to
the core’s performance include:
• Core operates at twice the bus speed (80960JD
only)
• Single-clock execution of most instructions
• Independent Multiply/Divide Unit
• Efficient instruction pipeline minimizes pipeline
break latency
• Register and resource scoreboarding allow
overlapped instruction execution
2
2.2
Burst Bus
A 32-bit high-performance bus controller interfaces
the 80960JD to external memory and peripherals.
The BCU fetches instructions and transfers data at
the rate of up to four 32-bit words per six clock
cycles. The external address/data bus is multiplexed.
PRELIMINARY
INTEL [ INTEL CORPORATION ]
