8086
WAVEFORMS (Continued)
MINIMUM MODE (Continued)
231455–14
SOFTWARE HALT–
e
DT/R
RD, WR, INTA
e
V
OH
INDETERMINATE
NOTES:
1. All signals switch between V
and V unless otherwise specified.
OL
OH
2. RDY is sampled near the end of T , T , T to determine if T machines states are to be inserted.
2
3
W
W
3. Two INTA cycles run back-to-back. The 8086 LOCAL ADDR/DATA BUS is floating during both INTA cycles. Control
signals shown for second INTA cycle.
4. Signals at 8284A are shown for reference only.
5. All timing measurements are made at 1.5V unless otherwise noted.
18
INTEL [ INTEL ]
