8086
A.C. CHARACTERISTICS (Continued)
TIMING RESPONSES
8086
8086-1
Min
8086-2
Min
Test
Symbol
Parameter
Units
Conditions
Min
10
Max
Max
Max
TCLAV Address Valid Delay
TCLAX Address Hold Time
110
10
10
10
50
10
10
60
ns
ns
ns
10
TCLAZ Address Float
Delay
TCLAX
80
40
TCLAX
50
TLHLL
ALE Width
TCLCH-20
TCLCH-10
TCLCH-10
ns
ns
ns
ns
TCLLH ALE Active Delay
TCHLL ALE Inactive Delay
80
85
40
45
50
55
TLLAX Address Hold Time TCHCL-10
TCHCL-10
10
TCHCL-10
10
e
20–100 pF
TCLDV Data Valid Delay
TCHDX Data Hold Time
10
10
110
50
60
ns *C
L
for all 8086
Outputs (In
addition to 8086
selfload)
10
10
ns
ns
TWHDX Data Hold Time
After WR
TCLCH-30
TCLCH-25
TCLCH-30
TCVCTV Control Active
Delay 1
10
10
10
0
110
110
110
10
10
10
0
50
45
50
10
10
10
0
70
60
70
ns
ns
ns
ns
TCHCTV Control Active
Delay 2
TCVCTX Control Inactive
Delay
TAZRL Address Float to
READ Active
TCLRL RD Active Delay
TCLRH RD Inactive Delay
10
10
165
150
10
10
70
60
10
10
100 ns
80
ns
ns
TRHAV RD Inactive to Next TCLCL-45
Address Active
TCLCL-35
TCLCL-40
TCLHAV HLDA Valid Delay
TRLRH RD Width
10
160
10
60
10
100 ns
2TCLCL-75
2TCLCL-60
TCLCH-60
2TCLCL-40
2TCLCL-35
TCLCH-35
2TCLCL-50
2TCLCL-40
TCLCH-40
ns
ns
ns
TWLWH WR Width
TAVAL Address Valid to
ALE Low
TOLOH Output Rise Time
TOHOL Output Fall Time
20
12
20
12
20
12
ns From 0.8V to 2.0V
ns From 2.0V to 0.8V
NOTES:
1. Signal at 8284A shown for reference only.
2. Setup requirement for asynchronous signal only to guarantee recognition at next CLK.
3. Applies only to T2 state. (8 ns into T3).
16
INTEL [ INTEL ]
