Front Side Bus Signal Quality Specifications
Table 3-1. Ringback Specifications for AGTL+ and GTL+ Asynchronous Signal Groups
Maximum Ringback
Notes
Signal Group
Transition
(with Input Diodes Present)
GTLREF + (0.06 * VTT
GTLREF - (0.06 * VTT
Unit
Figure
AGTL+, Async GTL+
AGTL+, Async GTL+
Low → High
High → Low
)
V
V
3-1
3-2
1,2,3,4,5,6
1,2,3,4,5,6
)
NOTES:
1. All signal integrity specifications are measured at the processor core (pads).
2. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
3. Specifications are for the edge rate of 1.8- 2.2V/ns.
4. All values specified by design characterization.
5. Please see Section 3.1.3 for maximum allowable overshoot.
6. The total ringback tolerance is 6% of VTT (0.06 * VTT). This consists of 4% AC and 2% DC components.
Ringback between GTLREF + (0.06 * VTT) and GTLREF - (0.06 * VTT) is not supported.
Figure 3-1. Low-to-High Front Side Bus Receiver Ringback Tolerance
VTT
+ 6% * VTT
Noise Margin
GTLREF
– 6% * VTT
VSS
Figure 3-2. High-to-Low Front Side Bus Receiver Ringback Tolerance
VTT
+ 6% * VTT
GTLREF
Noise Margin
- 6% * VTT
VSS
54
64-bit Intel® Xeon™ Processor MP with up to 8MB L3 Cache Datasheet
INTEL [ INTEL ]
