Electrical Specifications
Figure 2-2. Phase Lock Loop (PLL) Filter Requirements
0.2 dB
0 dB
-0.5 dB
forbidden
zone
-28 dB
forbidden
zone
-34 dB
DC
passband
1 Hz
fpeak
1 MHz 66 MHz
fcore
high frequency
band
NOTES:
1. Diagram not to scale.
2. No specification for frequencies beyond fcore (core frequency).
3. fpeak, if existent, should be less than 0.05MHz.
4. fcore represents the maximum core frequency supported by the platform.
2.2
Voltage Identification (VID)
The VID[5:0] pins supply the encodings that determine the voltage to be supplied by the V (the
CC
core voltage for the processor) voltage regulator. The VID specification for the processor is defined
by the Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 10.1
Design Guidelines, the Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down
(EVRD) 10.2 Design Guidelines, and the Voltage Regulator Module (VRM) 10.2L Design
Guidelines. Please refer to these documents for all VRM and VRD design issues. The voltage set
by the VID signals is the maximum V voltage allowed by the processor. VID signals are open
CC
drain outputs, which must be pulled up to V . Please refer to Table 2-13 for the DC specifications
TT
for these signals. A minimum V voltage is provided in Table 2-9 and changes with frequency.
CC
This allows processors running at a higher frequency to have a relaxed minimum V voltage
CC
specification. The specifications have been set such that one voltage regulator can work with all
supported frequencies.
20
64-bit Intel® Xeon™ Processor MP with up to 8MB L3 Cache Datasheet
INTEL [ INTEL ]
