Electrical Specifications
Note: Some AGTL+ signals do not include on-die termination (R ) and must be terminated on the
TT
motherboard. See Table 2-6 for details regarding these signals.
2.1.1
Front Side Bus Clock and Processor Clocking
BCLK[1:0] directly controls the front side bus interface speed as well as the core frequency of the
processor. The processor core frequency is a multiple of the BCLK[1:0] frequency. The processor
bus ratio multiplier will be set at its default ratio during manufacturing. The default setting
generates the maximum speed for the processor. It is possible to override this setting using
software. Refer to the Processor BIOS Writers Guide for details. This will permit operation at a
speed lower than the processor’s tested frequency.
The processor core frequency is configured during reset by using values stored internally during
manufacturing. The stored values set the highest bus fraction at which the particular processor can
operate. If lower speeds are desired, the appropriate bus ratio multiplier can be configured by
driving the A[21:16]# pins at reset. For details of operation at core frequencies lower than the
maximum rated processor speed, refer to the Processor BIOS Writers Guide.
The bus ratio multipliers supported are shown in Table 2-1. Other combinations will not be
validated or supported by Intel. For a given processor, only the ratios which result in a core
frequency equal to or less than the frequency marked on the processor are supported.
Table 2-1. Core Frequency to Front Side Bus Multiplier Configuration
Core
Frequency
to Front Side
Bus
Core
Frequency
A21#
A20#
A19#
A18#
A17#
A16#
Multiplier
1/16
1/17
1/18
1/19
1/20
1/22
2.66 GHz
2.83 GHz
3.00 GHz
3.16 GHz
3.33 GHz
3.66 GHz
L
L
L
L
L
L
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
H
L
L
H
H
L
L
H
L
H
H
H
L
NOTES:
1. Individual processors operate only at or below the frequency marked on the package.
2. Listed frequencies are not necessarily committed production frequencies.
3. For valid core frequencies of the processor, refer to the Processor Specification Update.
4. As described in Section 1.1, “H” refers to a high logic level (i.e. signal asserted) and “L” refers to a low logic
level (i.e. signal deasserted).
The processor uses a differential clocking implementation.
18
64-bit Intel® Xeon™ Processor MP with up to 8MB L3 Cache Datasheet
INTEL [ INTEL ]
