Electrical Specifications
2.1.2
Front Side Bus Clock Select (BSEL[1:0])
The BSEL[1:0] signals are used to select the frequency of the processor input clock (BCLK[1:0]).
Table 2-2 defines the possible combinations of the signals and the frequency associated with each
combination. The required frequency is determined by the processor, chipset, and clock
synthesizer. All processors must operate at the same front side bus frequency.
The processor operates at a 667 MHz front side bus frequency (selected by a 166 MHz BCLK[1:0]
frequency). Individual processors operate at the front side bus frequency specified by BSEL[1:0].
For more information about these pins, refer to Section 6.1.
Table 2-2. BSEL[1:0] Frequency Table for BCLK[1:0]
BSEL1
BSEL0
Function
0
0
1
1
0
1
0
1
RESERVED
RESERVED
RESERVED
166 MHz
2.1.3
Phase Lock Loop (PLL) Power and Filter
V
, V
, and V
are power sources required by the PLL clock generators on
CCA_CACHE
CCA
CCIOPLL
the processor. These are analog PLLs and they require low noise power supplies for minimum
jitter. These supplies must be low pass filtered from V .
TT
The AC low-pass requirements, with input at V , are as follows:
TT
• < 0.2 dB gain in pass band
• < 0.5 dB attenuation in pass band < 1 Hz
• > 34 dB attenuation from 1 MHz to 66 MHz
• > 28 dB attenuation from 66 MHz to core frequency
The filter requirements are illustrated in Figure 2-2.
64-bit Intel® Xeon™ Processor MP with up to 8MB L3 Cache Datasheet
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INTEL [ INTEL ]
