Signal Description
Table 2-11. Normal Functional Pin Straps (Sheet 2 of 3)
Strap Pin
Function
HPA_SLOT[2:0]
HPB_SLOT[2:0]
Hot Plug Mode / # of PCI Slots: Used in conjunction with HPx_SLOT[3] signal to
determine PCI Hot Plug Mode and number of PCI slots on a bus segment.
HPx_SLOT[3:0] = Hot Plug Mode Enable/Disable, # of PCI slots
0000 = hot plug disabled, 1 slot (optional)
0001 = hot plug disabled, 2 slots (optional)
0010 = hot plug disabled, 3 slots (optional)
0011 = hot plug disabled, 4 slots (optional)
0100 = hot plug disabled, 5 slots (optional)
0101 = hot plug disabled, 6 slots (optional)
0110 = hot plug disabled, 7 slots (optional)
0111 = hot plug disabled, 8 slots (optional)
1000 = reserved
1001 = hot plug enabled, 1 slot (parallel mode)
1010 = hot plug enabled, 2 slots (parallel mode)
1011 = hot plug enabled, 3 slots (serial mode)
1100 = hot plug enabled, 4 slots (serial mode)
1101 = hot plug enabled, 5 slots (serial mode)
1110 = hot plug enabled, 6 slots (serial mode)
1111 = hot plug enabled, 1 slot-no-glue (parallel mode)
PA133EN
PB133EN
Only relevant when Hot Plug Mode is disabled (HPx_SLOT[3] = 0) OR when in one-slot-
no-glue hot plug mode (HPx_SLOT[3:0] = 1111), AND when in PCI-X Mode
(PxPCIXCAP = 1).
133 MHz PCI-X Enable/Disable: Determines the maximum frequency (100 MHz or 133
MHz) of the PCI bus segment when in PCI-X Mode:
1 = 133 MHz PCI-X capable
0 = 100 MHz PCI-X max bus frequency
PAM66EN
PBM66EN
Only relevant when Hot Plug Mode is disabled (HPx_SLOT[3] = 0) OR when in one-slot-
no-glue hot plug mode (HPx_SLOT[3:0] = 1111) AND when in conventional PCI mode
(PxPCIXCAP = 0).
PCI 66 MHz Enable/Disable: Determines the maximum frequency (33 MHz or 66 MHz)
of the PCI bus segment when in conventional PCI mode:
1 = 66 MHz capable when in conventional PCI mode
0 = 33 MHz max frequency when in conventional PCI mode
Sampled on the rising edge of PWROK.
PASTRAP0
PBSTRAP0
Intel test mode:
1 = Reserved
0 = Normal operation
HAATNLED_1#/
CMODE
This pin strap is used to configure PCI Express** 1.0a support and is muxed with
HAATNLED_1#. The CMODE/HAATNLED_1# pin does not have ODT (On-Die
Termination). Please refer to the latest revision of the appropriate Platform Design Guide
for board implementation details.
30
Intel® 6700PXH 64-bit PCI Hub Datasheet
INTEL [ INTEL ]
