Intel® 6700PXH 64-bit PCI Hub Features
• PCI Express* Interface
• PCI standard Hot Plug
— Compatible with PCI Express Base
Specification 1.0a
— PCI Standard Hot-Plug controller Specification
Rev 1.0 compliant
— Compatible with PCI Express Base
Specification 1.0a
— PCI Standard Hot-Plug controller Specification
Rev 1.0 compliant
— Raw bit-rate on the data pins of 2.5 Gbit/s,
— Two controllers - one for each PCI bus segment
— Support for 6 slots maximum
resulting in a raw bandwidth per pin of 250 MB/
s
— Parallel mode operation for 1 and 2 slot systems
and slot interface logic not needed.
— x8 and x4 modes of operation, support for x4 on
3:0 (with 3 being lane 3) and 4:7 (with 4 being
lane 3)
— Serial mode operation for other systems with
hot-plug slots from 3 to 6. Slot interface logic
needed to serialize and de-serialize information
from Intel® 6700PXH 64-bit PCI Hub
— Support for x8, x4 lane reversal
— Support for x4 lane reversal only on the lower 4
lanes
— 1-slot-no-glue parallel mode operation when the
number of slots controlled is one and there are
no other devices on the PCI bus. No on-board Q-
Switches are needed for bus isolation in this
mode
— Maximum realized bandwidth (in x8 mode) on
PCI Express* interface is 2 GB/s in each
direction simultaneously, for an aggregate of 4
GB/s
— Full-speed self-test and diagnostic (IBIST)
functionality
• I/OXAPIC
— One I/OxAPIC controller per PCI bus segment
— 24 interrupts per controller
— Automatic link initialization, configuration and
re-training out of reset
— 16 physical PCI interrupt pins per PCI bus in the
server mode
— Runtime detection and recovery for loss of link
synchronization
— PCI virtual wire interrupt support via writing to
Pin Assertion Register in the I/OxAPIC
• PCI(X) Interface
— PCI Spec rev 2.3 compliant
— PCI-X 1.0b spec compliant
— 64-bit 66MHz, 3.3V
•
SMBus Interface
— Electrically compliant with System Management
Bus 2.0 Specification with PEC support
— Slave mode operation only
— 6 external REQ/GNT Pairs for internal arbiter
(only 3 pairs are available when operating SHPC
in parallel mode)
— Full read/write access to all configuration and
memory spaces in Intel® 6700PXH 64-bit PCI
Hub
— On-die termination of 8.33K ohms @ 40%
• Power Management
— 64 bit addressing, inbound and outbound and
support for DAC command
— Support for PCI Express* Active State Power
Management (ASPM) L0s link state
— Full peer-to-peer read and write capability
between the two PCI segments in Intel®
6700PXH 64-bit PCI Hub
— Support for PCI PM 1.1 compatible D0, D3hot
and D3cold device power states
— Support for PME# event propagation on behalf
of PCI devices
• RAS Features
— PCI Express* interfaces protected with 32-bit
CRC
— Full access to all registers via SMBus
— PCI bus protected with parity
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