SMBus Interface
Figure 7-2. SMBus Configuration Read (Write Bytes / Read Bytes, PEC Enabled)
S
S
S
S
X011_XXX
X011_XXX
X011_XXX
X011_XXX
W
W
W
W
A
A
A
A
Cmd = 10010000
Cmd = 00010000
Cmd = 00010000
Cmd = 01010000
A
A
A
A
Reserved
Device/Function
Register[15:8]
Register[7:0]
A
A
A
A
PEC
PEC
PEC
PEC
A
A
A
A
P
P
P
P
S
X011_XXX
X011_XXX
W
R
A
A
Cmd = 10010000
Status
A
A
Sr
PEC
PEC
PEC
PEC
PEC
N
N
N
N
N
P
P
P
P
P
S
X011_XXX
X011_XXX
W
R
A
A
Cmd = 00010000
Data[31:24]
A
A
Sr
S
X011_XXX
X011_XXX
W
R
A
A
Cmd = 00010000
Data[23:16]
A
A
Sr
S
X011_XXX
X011_XXX
W
R
A
A
Cmd = 00010000
Data[15:8]
A
A
Sr
S
X011_XXX
X011_XXX
W
R
A
A
Cmd = 01010000
Data[7:0]
A
A
Sr
7.1.3.2
Configuration Register Write Protocol
Configuration writes are accomplished through a series of SMBus writes. As with
configuration reads, a write sequence is first used to initialize the Bus Number, Device,
Function, and Register Number for the configuration access. The writing of this
information can be accomplished through any combination of the supported SMBus
write commands (Block, Word or Byte).
On SMBus, there is no concept of byte enables. Therefore, the Register Number written
to the slave is assumed to be aligned to the length of the Internal Command. In other
words, for a Write Byte internal command, the Register Number specifies the byte
address. For a Write DWord internal command, the two least-significant bits of the
Register Number are ignored. This is different from PCI where the byte enables are
used to indicate the byte of interest.
After all the information is set up, the SMBus master initiates one or more writes which
sets up the data to be written. The final write (End bit is set) initiates an internal
configuration write. If an error occurred, the SMBus interface NACKs the last write
operation just before the stop bit.
Examples of configuration writes are illustrated below. For the definition of the diagram
conventions below, refer to the SMBus Specification, Rev. 2.0.
Figure 7-3. SMBus Configuration Double Word Write (Block Write, PEC Enabled)
A
Data[31:24]
ByteCount =8
A
Reserved
A
Device/Function
Data[16:8]
A
Reg Number[15:8]
Data[7:0]
A
Reg Number [7:0]
PEC
S
X011_XXX
WA Cmd = 11011110
A
A
Data[23:16]
A
A
A
A P
80
Intel® 6400/6402 Advanced Memory Buffer Datasheet
INTEL [ INTEL ]
