SMBus Interface
7.1.3.1
Configuration Register Read Protocol
Configuration reads are accomplished through an SMBus write(s) and later followed by
an SMBus read. The write sequence is used to initialize the Bus Number, Device,
Function, and Register Number for the configuration access. The writing of this
information can be accomplished through any combination of the supported SMBus
write commands (Block, Word, or Byte). The Internal Command field for each write
should specify Read DWord.
After all the information is set up, the last write (End bit is set) initiates an internal
configuration read. If an error occurs during the internal access, the last write
command will receive a NACK. A status field indicates abnormal termination and
contains status information such as target abort, master abort, and time-outs. The
status field encoding is defined in the following table.
Table 7-3.
Status Field Encoding for SMBus Reads
Bit
Description
7
Reserved
6
Reserved
5
Reserved
4
Internal Target Abort
Reserved
3:1
0
Successful
Examples of configuration reads are illustrated below. All of these examples have PEC
(Packet Error Code) enabled. If the master does not support PEC, then bit 4 of the
command would be cleared and there would not be a PEC phase. For the definition of
the diagram conventions below, refer to the SMBus Specification, Rev. 2.0. For SMBus
read transactions, the last byte of data (or the PEC byte if enabled) is NACKed by the
master to indicate the end of the transaction. For diagram compactness, “Register
Number[]” is also sometimes referred to as “Reg Number” or “Reg Num”.
Figure 7-1. SMBus Configuration Read (Block Write / Block Read, PEC Enabled)
S
X011_XXX
W A
Cmd = 11010010
A
Byte Count = 4
A
Reserved
A
Device/Function
A
Reg Number[15:8]
A
Reg Number [7:0]
A
PEC
A P
S
X011_XXX
X011_XXX
W A
Cmd = 11010010
Byte Count = 5
A
A
Sr
R
A
Status
A
A
Data[31:24]
Data[7:0]
A
A
Data[23:16]
A
N P
PEC
Data[15:8]
The following example uses byte reads.
Intel® 6400/6402 Advanced Memory Buffer Datasheet
79