Errors
Configuration Register Access error has been flagged (and matching address logged),
the log registers for that error remain locked until either 1) that bit in the FERR and/or
NERR cleared or 2) a power-up reset.
6.3
Fail Over Mode Support
The AMB supports single lane Fail Over mode as described in the
FB DIMM Architecture
and Protocol Specification,.
This is done under host control or through the SMBus.
6.4
Failback to Pass-Thru
In general, the AMB attempts to minimize the number of Single Points Of Failure
(SPOF) that could bring down the entire channel. Errors in any one lane can be mapped
out with Fail Over. Errors on the DDR interface can be handled by disabling the DRAM
interface and leaving the AMB in a repeater like mode. The goal is to allow the system
(following a reset or fast reset sequence) to work around the bad DIMM and keep the
DIMMs downstream in operation until there is time for system maintenance.
A AMB in an intermediate DIMM should continue to operate in pass-thru mode so that
NB and SB data are relayed to the next links in the channel with minimal functionality.
Only the following parts of the AMB need to be healthy to support this mode:
• Clock inputs and PLL circuitry to generate FBD clocks
• Minimal core logic around FBD I/O enabling and reset
— Reset generation
— Bit lock detection.
• at least N-1 FBD lanes operational in NB and SB channels
§
Intel® 6400/6402 Advanced Memory Buffer Datasheet
75
INTEL [ INTEL CORPORATION ]
