Errors
6.1.1.2
Table 6-2.
Errors during Channel Operation
Link Errors in Normal Operation (Sheet 1 of 2)
Error
Response
If CMDCRC error type enabled in EMASK Register
1.
No command executed
2.
120-bit Raw SB Frame captured in RECFBD Error Log Registers
3.
Type of error logged in FERR/NERR registers
4.
Error/Alert Asserted bit set in FBD Status 0 register
5.
Ignore future commands except Soft Channel Reset until Soft Channel Reset or
Link Reset Received
6.
Alert Frame sent continuously starting with NB frame in which returned data
pattern would be sent if aborted command had been a config read. Alert
patterns continue until Soft Channel Reset or Link Fast Reset received.
Note:
Will NOT close DRAM pages or place DRAM into Self Refresh until detection
of Link Reset.
Else ignore error
If FEWEDGES error type enabled in EMASK Register
1.
No command executed in expected Sync slot
2.
120 bit Raw SB Frame captured in RECFBD Error Log Registers
3.
Type of error logged in FERR/NERR registers
4.
Error/Alert Asserted bit set in FBD Status 0 register
5.
DDR Self Refresh FSM triggered to put DRAMs into Self Refresh
6.
Ignore future commands including Soft Channel Reset until Link Reset
Received
7.
Alert Frame sent continuously starting with NB frame in which returned data
pattern would be sent if aborted command had been a config read. Alert
patterns continue until Link Fast Reset received.
Else ignore error
Overwriting the write buffer is a host error. The AMB does not take any action based
on an overrun. DRAM writes will proceed. What data item is written following an
overrun condition is not defined.
An overrun could be the result of channel errors, but these errors are detectable by
other means. Detection of an overrun condition is not required, but may be done by
implementation dependent means for debug.
Underrunning the write buffer is a host error. The AMB does not take any action
based on an underrun. DRAM writes will proceed. What data item is written
following an underrun condition is not defined.
An underrun could be the result of channel errors, but these errors are detectable
by other means. Detection of an underrun condition is not required, but may be
done by implementation dependent means for debug.
CRC Error on SB frame
“A” Command - detected by 14-bit CRC (or
reduced 10-bit CRC in Fail Over mode)
or
CRC Error on SB data or “BC” Commands
in Command Frame - detected by 22-bit
CRC (or reduced 10bit CRC in Fail Over
mode
Lose transition density on channel as
detected by no Sync in within 2 times the
SYNCTRAININT value (typically last 84
frames).
Note:
Purpose of this error is not to
detect violation of required
transition density (6 out of 512)
but to detect hang in the host and
put DRAM into self refresh. Any
corruption caused by lack of
transitions will be detected by
CRC violations.
Write Buffer Overrun
Write data received when FIFO is full
Write Buffer Underrun:
not enough valid entries in Write FIFO to
support write data to memory
72
Intel® 6400/6402 Advanced Memory Buffer Datasheet
INTEL [ INTEL CORPORATION ]
