Glossary
Term
Definition
POR
Plan Of Record
Primary
PTH
In the direction towards the Host controller
Plated Through-Hole
PVT
Process, Voltage and Temperature
Rank
A DIMM is organized as one or two physical sets of memory, called ranks. Note
that single rank or dual rank is different from single-sided or double-sided, for
example, a single rank DIMM build from x4 DRAM devices is actually double-
sided. It is also common practice to distribute the 9 devices of an x8 DIMM
between both sides of the DIMM to enhance the thermal performance of the
module. The standard 4-slot DDR2 topology is limited to single rank DIMM due
to loading constraints.
RAS
Reliability, Availability, Serviceability. (also: Row Address Strobe - meaning is
context dependent.)
Resample
A resampler is a serial data in and serial data out node that attenuates jitter by
regenerating the serial data using a clock recovered from the incoming data
stream derived from a common reference clock. It also resets the voltage
budget of the retransmitted data.
Resync
A resync repeater is a serial data in and serial data out node that resynchronizes
data to a local clock after it has been sampled with a recovered clock derived
from a common reference clock. The local clock is also generated from the same
reference clock by a PLL multiplier. A drift compensation buffer is inserted
between the two clock domains which absorbs the maximum link delay change
over worst case voltage and temperature changes. Both the jitter and voltage
budgets for the retransmitted data are reset.
RPD
Return Path Discontinuity
SB
Southbound
SBI
Southbound Interface. (also: Southbound link control logic)
Single Data Rate
SDR
SDRAM
Secondary
Synchronous Dynamic Random Access Memory
In the direction away from the Host controller
Seed, SEED
The starting or “seed” value used to algorithmically generate pseudo-random
data. Usually in reference to a LFSR implementation.
Serial Present Detect (aka
SMBus protocol
A 2-signal serial bus used to read and write control registers in the AMB and
SDRAM
SI
Signal Integrity
SMBus, SMBUS
System Management Bus. Mastered by a system management controller to read
and write configuration registers. Limited to 100 kHz.
Southbound
SPD
The direction of signals running from the host controller toward the DIMMs.
Serial Presence Detect. Usually in reference to the serial ROM on a socketable
DIMM which contains information specific to the unit.
SPOF
Single Point Of Failure
SSC
Spread Spectrum Clocking. Usually used to lower average EM emissions.
Simultaneously Switching Outputs
SSO
SSTL_18
Throttled
Series Stub Terminated Logic for 1.8 V
Temporarily prohibiting memory accesses when a thermal or electrical limit has
been reached.
Transparent Mode
High speed FBD linked I/Os are bypassed with lower speed CMOS I/Os to allow
lower speed tester to control and test DRAMs on the DIMM.
Unit Interval
VCO
Average time interval between voltage transitions of a signal
Voltage Controlled Oscillator
V
V
I/O buffer voltage for DDR2 buffers. Nominally 1.8 V
Ground (0.0 V)
DDQ
SS
Intel® 6400/6402 Advanced Memory Buffer Datasheet
249
INTEL [ INTEL ]
