Glossary
Term
EM
EMI
FBD
FBD Channel
FBDIMM
FERR
FIFO
Frame
FSM
HCSL
Host
IBIST
I/O
ISI
JEDEC
JESD79
JTAG
LA
LAI
Lane
LFSR
Link
MC
MemBIST
Mesochronous
MTBF
MT/s
NACK
NB
NBI
NERR
Northbound
ODT
Page Replace aka Page
Miss, Row Hit / Page Miss
Page Hit
Page Miss (Empty Page)
PEC
Plesiochronous
PLL
Electromagnetic
Electromagnetic interference
Fully-Buffered DIMM
Definition
Combination of 10 lane Southbound Links and 13 or 14 lane Northbound Links
that make up a logical memory channel from host perspective
Fully-Buffered DIMM
First Error
First-In, First-Out. Usually in reference to a buffer implementation.
Group of bits containing commands or data
Finite State Machine
High-speed Current Steering Logic
Memory controller agent on an FBD channel
Interconnect Built-In Self-Test (built-in interconnect test)
Input Output. Usually in reference to a bidirectional buffer cell or circuit.
Inter Symbol Interference – see section “Initialization / Clocking” for definition
JEDEC Solid State Technology Association (once known as the Joint Electron
Device Engineering Council)
JEDEC Standard 79,
DDR SDRAM Specification
Joint Test Action Group. Usually in reference to the IEEE 1149.1a boundary scan
test standard.
Logic Analyzer
Logic Analyzer Interface
Differential pair of receivers or transmitters
Linear Feedback Shift Register. Usually in reference to pseudo-random bit-
stream data.
High speed parallel Differential Point-to-Point interface
Memory interface Control (block)
Memory Built-In Self-Test
Small ppm frequency difference.
Mean Time Between Failures
Mega Transfers per Second
Not-ACKnowledge. Usually in reference to SMBus communications.
Northbound
Northbound Interface. (also: Northbound link control logic)
Next/Subsequent Error
The direction of signals running from the furthest DIMM toward the host.
On-Die Termination
An access to a row that has another page open. The page must be transferred
back from the sense amps to the array, and the bank must be precharged.
An access to an open page, or DRAM row. The data can be supplied from the
sense amps at low latency.
An access to a page that is not buffered in sense amps and must be fetched
from DRAM array.
Packet Error Code
Having the same frequency but arbitrary phase differences.
Phase Locked Loop
248
Intel® 6400/6402 Advanced Memory Buffer Datasheet
INTEL [ INTEL CORPORATION ]
