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6400 参数 Datasheet PDF下载

6400图片预览
型号: 6400
PDF下载: 下载PDF文件 查看货源
内容描述: 高级内存缓冲器 [Advanced Memory Buffer]
分类和应用:
文件页数/大小: 250 页 / 3863 K
品牌: INTEL [ INTEL ]
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Glossary  
A Glossary  
A.1  
Terms and Definitions  
Term  
Definition  
ADC  
Analog to Digital Converter  
Advanced Memory Buffer  
Autonomous Platform Manager  
Automatic Test Equipment  
Built-In Self-Test  
AMB  
APM  
ATE  
BIST  
BL4/BL8  
CAS  
DRAM Burst Length 4/8  
Column Address Strobe  
Chip Boot Configuration  
CBC  
Chip disable  
An ECC encoding specifically tailored for memory such that the data from any  
defective memory device can be reconstructed from some aggregate of  
surviving memory devices. Corrects data from failed device. The AMB employs  
an “x8” ECC, which means that all data from a partially or completely failed 8-bit  
device can be recovered without stopping the system. This same ECC provides  
the same level of coverage for 4-bit (“x4”) devices.  
CRC  
Cyclic Redundancy Code(s). Usually in reference to binary error detection  
algorithms.  
CSR  
Configuration and Status Register(s)  
Double Data Rate (SDRAM)  
DDR  
DDR Branch  
The minimum aggregation of DDR channels which operate in lock-step to  
support error correction. Two channels per branch supports x8 chip disable ECC.  
A rank spans a branch.  
DDR Channel  
A DDR channel consists of a data channel with 72 bits of data and an ADDR/  
CNTRL channel  
DDR Data channel  
A DDR data channel consists of 72 bits of data, divided into 18 data groups  
Each data group consists of 4 data signals and a differential strobe pair  
Design for Test/Manufacturability/Validation  
DDR Data group  
DFx  
DFV  
Design For Validation  
DIMM  
Dual In-Line Memory Module. A packaging arrangement of memory devices on a  
socketable substrate.  
DIMM Slot  
Receptacle (socket) for a DIMM. Also, the relative physical location of a specific  
DIMM on a DDR channel.  
DIMM Stack  
Dual-ranked x4 DRAM DIMM physical topology: refers to two physical rows of  
DRAM “stacked” one above another  
DLL  
Delay locked loop  
DPM  
Defects per million  
DRAM  
Dynamic Random Access Memory  
The DRAM cells selected by the Row Address  
Error Correction Code. For the AMB, this is a chip disable code.  
Electrically Erasable Programmable Read Only Memory  
Error Mask  
DRAM Page (Row)  
ECC  
EEPROM  
EMask, EMASK  
Intel® 6400/6402 Advanced Memory Buffer Datasheet  
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