Introduction
Figure 1-2. AMB Interfaces
MEMORY INTERFACE
NB FBD
Out Link
NB FBD
In Link
AMB
SB FBD
Out Link
SB FBD
InLink
SMB
1.3.1
FBD High-Speed Differential Point-to-Point Link (at 1.5 V)
Interfaces
The AMB supports one FBD Channel interface consisting of two bidirectional link
interfaces using high-speed differential point-to-point electrical signaling.
The southbound input link is 10 lanes wide and carries commands and write data from
the host memory controller or the first adjacent DIMM in the host direction. The
southbound output link forwards this same data to the next adjacent FBD.
The northbound input link is 13 to 14 lanes wide and carries read return data or status
information from the next FB DIMM in the chain back towards the host. The northbound
output link forwards this information back towards the host and multiplexes in any read
return data or status information that is generated internally.
1.3.2
DDR2 Channel
The DDR2 channel on the AMB supports direct connection to DDR2 SDRAMs. The DDR2
channel supports two ranks of eight banks with 16 row/column request, 64 data
signals, and eight check-bit signals. There are two copies of address and command
signals to support DIMM routing and electrical requirements. Four-transfer bursts are
driven on the data and check-bit lines at 800 MHz.
Propagation delays between read data/check-bit strobe lanes on a given channel can
differ. Each strobe can be calibrated by hardware state machines using write/read trial
and error. Hardware aligns the read data and check-bits to a single core clock.
The AMB provides four copies of the command clock phase references (CLK[3:0]) and
write data/check-bit strobes (DQSs) for each DRAM nibble.
1.3.3
SMBus Slave Interface
The AMB supports an SMBus interface to allow system access to configuration registers
independent of the FBD link. The AMB will never be a master on the SMBus, only a
slave. Serial SMBus data transfer is supported at 100 kHz.
14
Intel® 6400/6402 Advanced Memory Buffer Datasheet
INTEL [ INTEL ]
