Electrical Characteristics
Page 9
I/O Pin Leakage Current
Table 9
lists the Stratix V I/O pin leakage current specifications.
Table 9. I/O Pin Leakage Current for Stratix V Devices
Symbol
I
I
I
OZ
Description
Input pin
Tri-stated I/O pin
Conditions
V
I
= 0 V to V
CCIOMAX
V
O
= 0 V to V
CCIOMAX
Min
–30
–30
Typ
—
—
Max
30
30
Unit
µA
µA
Note to
Table 9:
(1) If V
O
= V
CCIO
to V
CCIOMax
, 100 µA of leakage current per I/O is expected.
Bus Hold Specifications
Table 10
lists the Stratix V device family bus hold specifications.
Table 10. Bus Hold Parameters for Stratix V Devices
V
CCIO
Parameter Symbol
Conditions
1.2 V
Min
Low
sustaining
current
High
sustaining
current
Low
overdrive
current
High
overdrive
current
Bus-hold
trip point
I
SUSL
V
IN
> V
IL
(maximum)
V
IN
< V
IH
(minimum)
0V < V
IN
<
V
CCIO
0V < V
IN
<
V
CCIO
—
22.5
Max
—
1.5 V
Min
25.0
Max
—
1.8 V
Min
30.0
Max
—
2.5 V
Min
50.0
Max
—
3.0 V
Min
70.0
Max
—
µA
Unit
I
SUSH
–22.5
—
–25.0
—
–30.0
—
–50.0
—
–70.0
—
µA
I
ODL
—
120
—
160
—
200
—
300
—
500
µA
I
ODH
V
TRIP
—
–120
—
–160
—
–200
—
–300
—
–500
µA
0.45
0.95
0.50
1.00
0.68
1.07
0.70
1.70
0.80
2.00
V
On-Chip Termination (OCT) Specifications
If you enable OCT calibration, calibration is automatically performed at power-up for
I/Os connected to the calibration block.
Table 11
lists the Stratix V OCT termination
calibration accuracy specifications.
Table 11. OCT Calibration Accuracy Specifications for Stratix V Devices
(1)
(Part 1 of 2)
Calibration Accuracy
Symbol
Description
Internal series termination
with calibration (25-
setting)
Conditions
C1
V
CCIO
= 3.0, 2.5,
1.8, 1.5, 1.2 V
C2,I2
C3,I3,
I3YY
±15
Unit
C4,I4
25- R
S
±15
±15
±15
%
December 2015
Altera Corporation
Stratix V Device Datasheet
INTEL [ INTEL CORPORATION ]
