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Electrical Characteristics
Table 13. OCT Variation after Power-Up Calibration for Stratix V Devices (Part 2 of 2) (1)
Symbol
Description
VCCIO (V)
3.0
Typical
0.189
0.208
0.266
0.273
0.317
Unit
2.5
OCT variation with temperature
without recalibration
dR/dT
1.8
%/°C
1.5
1.2
Note to Table 13:
(1) Valid for a VCCIO range of 5% and a temperature range of 0° to 85°C.
Pin Capacitance
Table 14 lists the Stratix V device family pin capacitance.
Table 14. Pin Capacitance for Stratix V Devices
Symbol
Description
Value
Unit
pF
CIOTB
Input capacitance on the top and bottom I/O pins
Input capacitance on the left and right I/O pins
6
6
6
CIOLR
COUTFB
pF
Input capacitance on dual-purpose clock output and feedback pins
pF
Hot Socketing
Table 15 lists the hot socketing specifications for Stratix V devices.
Table 15. Hot Socketing Specifications for Stratix V Devices
Symbol
IIOPIN (DC)
Description
DC current per I/O pin
Maximum
300 A
8 mA (1)
100 mA
50 mA
IIOPIN (AC)
AC current per I/O pin
IXCVR-TX (DC)
DC current per transceiver transmitter pin
DC current per transceiver receiver pin
IXCVR-RX (DC)
Note to Table 15:
(1) The I/O ramp rate is 10 ns or more. For ramp rates faster than 10 ns, |IIOPIN| = C dv/dt, in which C is the I/O pin
capacitance and dv/dt is the slew rate.
Stratix V Device Datasheet
December 2015 Altera Corporation
INTEL [ INTEL ]
