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5M80ZT100C5N 参数 Datasheet PDF下载

5M80ZT100C5N图片预览
型号: 5M80ZT100C5N
PDF下载: 下载PDF文件 查看货源
内容描述: [Flash PLD, 14ns, 64-Cell, CMOS, PQFP100, 16 X 16 MM, 0.50 MM PITCH, LEAD FREE, TQFP-100]
分类和应用: 时钟可编程逻辑
文件页数/大小: 166 页 / 4004 K
品牌: INTEL [ INTEL ]
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Chapter 7: User Flash Memory in MAX V Devices  
7–11  
UFM Operating Modes  
Erase  
The ERASEsignal initiates an erase sequence to erase one sector of the UFM. The data  
register is not needed to perform an erase sequence. To indicate the sector of the UFM  
to be erased, the MSB of the address register should be loaded with 0 to erase UFM  
sector 0, or 1 to erase UFM sector 1 (Figure 7–2 on page 7–5). On a rising edge of the  
ERASEsignal, the memory sector indicated by the MSB of the address register will be  
erased. The BUSYsignal is asserted until the erase sequence is completed. The address  
register should not be modified until the BUSYsignal is de-asserted to prevent the flash  
content from being corrupted. This ERASEsignal is ignored when the BUSYsignal is  
asserted. Figure 7–8 illustrates the UFM waveforms during erase mode.  
1
When the UFM sector is erased, it has 16-bit locations all filled with FFFF. Each UFM  
storage bit can be programmed only once between erase sequences. You can write to  
any word up to two times providing the second programming attempt at that location  
only adds 0s. 1s are mask bits for your input word that cannot overwrite 0s in the  
flash array. New 1s in the location can only be achieved by an erase. Therefore, it is  
possible for you to perform byte writes because the UFM array is 16 bits for each  
location.  
Figure 7–8. UFM Erase Waveforms  
ARSHFT  
ARCLK  
ARDin  
9 Address Bits  
tACLK  
tAH  
tASU  
tADH  
tADS  
DRSHFT  
DRCLK  
DRDin  
DRDout  
OSC_ENA  
tOSCS  
tOSCH  
PROGRAM  
ERASE  
tEB  
tBE  
BUSY  
tEPMX  
January 2011 Altera Corporation  
MAX V Device Handbook