Chapter 7: User Flash Memory in MAX V Devices
7–13
Software Support for UFM Block
Software Support for UFM Block
The Altera Quartus II software includes sophisticated tools that fully utilize the
advantages of the UFM block in MAX V devices, while maintaining simple, easy-to-
use procedures that accelerate the design process. The following section describes
how the ALTUFM megafunction supports a simple design methodology for
instantiating standard interface protocols for the UFM block, such as:
■
■
■
■
I2C
SPI
Parallel
None (Altera Serial Interface)
This section includes the megafunction symbol, the input and output ports, and a
description of the MegaWizard Plug-In Manager options. Refer to Quartus II Help for
the ALTUFM megafunction Altera Hardware Description Language (AHDL)
functional prototypes (applicable to Verilog HDL), VHDL component declarations,
and parameter descriptions. You can access this megafunction from the Memory
Compiler directory on page 2a of the MegaWizard Plug-In Manager.
The ALTUFM MegaWizard Plug-In Manager has separate pages that apply to the
MAX V UFM block. During compilation, the Quartus II Compiler verifies the
ALTUFM parameters selected against the available logic array interface options, and
any specific assignments.
Inter-Integrated Circuit
Inter-Integrated Circuit (I2C) is a bidirectional two-wire interface protocol, requiring
only two bus lines: a serial data/address line (SDA), and a serial clock line (SCL).
Each device connected to the I2C bus is software addressable by a unique address. The
I2C bus is a multi-master bus where more than one integrated circuit (IC) capable of
initiating a data transfer can be connected to it, which allows masters to function as
transmitters or receivers.
The ALTUFM_I2C megafunction features a serial, 8-bit bidirectional data transfer up
to 100 Kbits per second. With the ALTUFM_I2C megafunction, the MAX V UFM and
logic can be configured as a slave device for the I2C bus. The ALTUFM megafunction’s
I2C interface is designed to function similar to I2C serial EEPROMs.
The Quartus II software supports four different memory sizes:
■
■
■
■
(128 × 8) 1 Kbits
(256 × 8) 2 Kbits
(512 × 8) 4 Kbits
(1,024 × 8) 8 Kbits
I2C Protocol
The following defines the characteristics of the I2C bus protocol:
■
Only two bus lines are required: SDA and SCL. Both SDA and SCL are
bidirectional lines that remain high when the bus is free.
January 2011 Altera Corporation
MAX V Device Handbook
INTEL [ INTEL ]
