欢迎访问ic37.com |
会员登录 免费注册
发布采购

5M80ZT100C5N 参数 Datasheet PDF下载

5M80ZT100C5N图片预览
型号: 5M80ZT100C5N
PDF下载: 下载PDF文件 查看货源
内容描述: [Flash PLD, 14ns, 64-Cell, CMOS, PQFP100, 16 X 16 MM, 0.50 MM PITCH, LEAD FREE, TQFP-100]
分类和应用: 时钟可编程逻辑
文件页数/大小: 166 页 / 4004 K
品牌: INTEL [ INTEL ]
 浏览型号5M80ZT100C5N的Datasheet PDF文件第107页浏览型号5M80ZT100C5N的Datasheet PDF文件第108页浏览型号5M80ZT100C5N的Datasheet PDF文件第109页浏览型号5M80ZT100C5N的Datasheet PDF文件第110页浏览型号5M80ZT100C5N的Datasheet PDF文件第112页浏览型号5M80ZT100C5N的Datasheet PDF文件第113页浏览型号5M80ZT100C5N的Datasheet PDF文件第114页浏览型号5M80ZT100C5N的Datasheet PDF文件第115页  
Chapter 7: User Flash Memory in MAX V Devices  
7–7  
UFM Functional Description  
Oscillator  
OSC_ENA, one of the input signals in the UFM block, is used to enable the oscillator  
signal to output through the OSCoutput port. You can use this OSCoutput port to  
connect with the interface logic in the logic array. It can be routed through the logic  
array and fed back as an input clock for the address register (ARCLK) and the data  
register (DRCLK). The output frequency of the OSCport is one-fourth that of the  
oscillator frequency. As a result, the frequency range of the OSCport is 3.9 to 5.3 MHz.  
The maximum clock frequency accepted by ARCLKand DRCLKis 10 MHz and the duty  
cycle accepted by the DRCLKand ARCLKinput ports is approximately 45% to 50%.  
When the OSC  
_
ENAinput signal is asserted, the oscillator is enabled and the output is  
ENAsignal is set low,  
routed to the logic array through the OSCoutput. When the OSC  
_
the OSCoutput drives constant high. The routing delay from the OSCport of the UFM  
block to OSCoutput pin depends on placement. You can analyze this delay using the  
TimeQuest timing analyzer.  
The undivided internal oscillator, which is not accessible, operates in a frequency  
range from 15.6 to 21.2 MHz. The internal oscillator is enabled during power-up,  
in-system programming, and real-time ISP. At all other times, the oscillator is not  
running unless the UFM is instantiated in the design and the OSC  
To see how specific operating modes of the ALTUFM megafunction handle OSC  
_
ENAport is asserted.  
ENA  
_
and the oscillator, refer to “Software Support for UFM Block” on page 7–13. For user-  
generated logic interfacing to the UFM, the oscillator must be enabled during  
program or erase operations, but not during read operations. The OSC_ENAsignal can  
be tied low if you are not issuing any PROGRAM or ERASE commands.  
1
1
During real-time ISP operation, the internal oscillator automatically enables and  
outputs through the OSCoutput port (if this port is instantiated) even though the  
OSC_ENAsignal is tied low. You can use the RTP_BUSYsignal to detect the beginning and  
ending of the real-time ISP operation for gated control of this self-enabled OSCoutput  
condition.  
The internal oscillator is not enabled all the time. The internal oscillator for the  
program or erase operation is only activated when the flash memory block is being  
programmed or erased. During a read operation, the internal oscillator is activated  
whenever the flash memory block is reading data.  
Instantiating the Oscillator without the UFM  
You can use the MAX II/MAX V Oscillator megafunction selection in the  
MegaWizardPlug-In Manager to instantiate the UFM oscillator if you intend to use  
this signal without using the UFM memory block. Figure 7–4 shows the  
ALTUFM_OSC megafunction instantiation in the Quartus II software.  
Figure 7–4. The Quartus II ALTUFM_OSC Megafunction  
January 2011 Altera Corporation  
MAX V Device Handbook