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5CSEMA6F31C8N 参数 Datasheet PDF下载

5CSEMA6F31C8N图片预览
型号: 5CSEMA6F31C8N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 110000-Cell, CMOS, PBGA896, ROHS COMPLIANT, FBGA-896]
分类和应用: 可编程逻辑
文件页数/大小: 66 页 / 1360 K
品牌: INTEL [ INTEL ]
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Electrical Characteristics  
Page 13  
Table 16. Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications for Cyclone V Devices (Part 2 of 2)  
VIL(DC) (V)  
Max  
VIH(DC) (V)  
VIL(AC) (V)  
Max  
VIH(AC) (V)  
Min  
VOL (V)  
Max  
VOH (V)  
Min  
(1)  
(1)  
I/O  
Iol  
Ioh  
Standard  
(mA)  
(mA)  
Min  
Min  
Max  
SSTL-135  
SSTL-125  
VREF – 0.09 VREF + 0.09  
VREF – 0.85 VREF + 0.85  
VREF – 0.16 VREF + 0.16 0.2 x VCCIO 0.8 x VCCIO  
VREF – 0.15 VREF + 0.15 0.2 x VCCIO 0.8 x VCCIO  
HSTL-18  
Class I  
V
V
V
V
REF – 0.1  
REF – 0.1  
REF – 0.1  
REF – 0.1  
VREF + 0.1  
VREF + 0.1  
VREF + 0.1  
VREF + 0.1  
VREF – 0.2  
VREF – 0.2  
VREF – 0.2  
VREF – 0.2  
VREF + 0.2  
VREF + 0.2  
VREF + 0.2  
VREF + 0.2  
0.4  
0.4  
0.4  
0.4  
VCCIO – 0.4  
VCCIO – 0.4  
VCCIO – 0.4  
VCCIO – 0.4  
8
16  
8
–8  
–16  
–8  
HSTL-18  
Class II  
HSTL-15  
Class I  
HSTL-15  
Class II  
16  
8
–16  
–8  
HSTL-12  
Class I  
–0.1  
5
VREF – 0.08 VREF + 0.08 VCCIO + 0.15 VREF – 0.15 VREF + 0.15 0.25 x VCCIO 0.75 x VCCIO  
HSTL-12  
Class II  
–0.1  
5
V
V
REF – 0.08 VREF + 0.08 VCCIO + 0.15 VREF – 0.15 VREF + 0.15 0.25 x VCCIO 0.75 x VCCIO  
16  
–16  
HSUL-12  
REF – 0.13 VREF + 0.13  
VREF – 0.22 VREF + 0.22 0.1 x VCCIO 0.9 x VCCIO  
Note to Table 16:  
(1) To meet the IOL and IOH specifications, you must set the current strength settings accordingly. For example, to meet the SSTL15CI specification (8 mA), you  
should set the current strength settings to 8 mA. Setting at lower current strength may not meet the IOL and IOH specifications in the handbook.  
Table 17. Differential SSTL I/O Standards for Cyclone V Devices  
VCCIO (V)  
Typ  
VSWING(DC) (V)  
VX(AC) (V)  
Typ  
VSWING(AC) (V)  
Min Max  
I/O Standard  
Min  
Max  
Min  
Max  
Min  
Max  
VCCIO  
0.6  
+
VCCIO/2–  
0.2  
V
V
V
V
V
CCIO/2+  
0.2  
SSTL-2 Class I, II  
2.375  
2.5  
1.8  
1.5  
2.625  
0.3  
0.62  
0.5  
V
V
CCIO + 0.6  
CCIO + 0.6  
VCCIO  
0.6  
+
VCCIO/2–  
0.175  
CCIO/2+  
0.175  
SSTL-18 Class I, II 1.71  
SSTL-15 Class I, II 1.425  
1.89  
1.575  
1.45  
0.25  
0.2  
VCCIO/2–  
0.15  
CCIO/2+ 2(VIH(AC)  
0.15 VREF  
2(VIL(AC)  
VREF  
(1)  
(1)  
(1)  
)
)
VCCIO/2–  
0.15  
CCIO/2+ 2(VIH(AC)  
0.15 VREF  
2(VIL(AC)  
VREF  
SSTL-135  
1.283 1.35  
0.18  
0.18  
V
CCIO/2  
CCIO/2  
)
)
VCCIO/2–  
0.15  
CCIO/2+ 2(VIH(AC)  
0.15 VREF  
2(VIL(AC)  
VREF  
SSTL-125  
1.19  
1.25  
1.31  
V
)
)
Note to Table 17:  
(1) The maximum value for VSWING(DC) is not defined. However, each single-ended signal needs to be within the respective single-ended limits  
(VIH(DC) and VIL(DC)).  
July 2014 Altera Corporation  
Cyclone V Device Datasheet