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5CSEBA6U19I7LN 参数 Datasheet PDF下载

5CSEBA6U19I7LN图片预览
型号: 5CSEBA6U19I7LN
PDF下载: 下载PDF文件 查看货源
内容描述: [Cyclone V Device Datasheet]
分类和应用:
文件页数/大小: 93 页 / 945 K
品牌: INTEL [ INTEL ]
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Cyclone V Device Datasheet  
CV-51002 | 2019.01.25  
Symbol  
Parameter  
Condition  
Min  
10  
Typ  
Max  
Unit  
tPLL_PSERR  
tARESET  
Accuracy of PLL phase shift  
±50  
ps  
ns  
Minimum pulse width on the areset signal  
Input clock cycle-to-cycle jitter  
(56)(57)  
tINCCJ  
FREF ≥ 100 MHz  
FREF < 100 MHz  
FOUT ≥ 100 MHz  
FOUT < 100 MHz  
FOUT ≥ 100 MHz  
FOUT < 100 MHz  
FOUT ≥ 100 MHz  
FOUT < 100 MHz  
FOUT ≥ 100 MHz  
FOUT < 100 MHz  
FOUT ≥ 100 MHz  
FOUT < 100 MHz  
0.15  
UI (p-p)  
ps (p-p)  
ps (p-p)  
mUI (p-p)  
ps (p-p)  
mUI (p-p)  
ps (p-p)  
mUI (p-p)  
ps (p-p)  
mUI (p-p)  
ps (p-p)  
±750  
(58)  
tOUTPJ_DC  
Period jitter for dedicated clock output in  
integer PLL  
300  
30  
425(61), 300(59)  
42.5(61), 30(59)  
300  
(58)  
tFOUTPJ_DC  
Period jitter for dedicated clock output in  
fractional PLL  
(58)  
tOUTCCJ_DC  
Cycle-to-cycle jitter for dedicated clock output  
in integer PLL  
30  
(58)  
tFOUTCCJ_DC  
Cycle-to-cycle jitter for dedicated clock output  
in fractional PLL  
425(61), 300(59)  
42.5(61), 30(59)  
650  
(58)(60)  
tOUTPJ_IO  
Period jitter for clock output on a regular I/O  
in integer PLL  
65  
mUI (p-p)  
continued...  
(56)  
A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source with  
jitter < 120 ps.  
(57)  
(58)  
FREF is fIN/N, specification applies when N = 1.  
Peak-to-peak jitter with a probability level of 10–12 (14 sigma, 99.99999999974404% confidence level). The output jitter specification  
applies to the intrinsic jitter of the PLL, when an input jitter of 30 ps is applied. The external memory interface clock output jitter  
specifications use a different measurement method and are available in Memory Output Clock Jitter Specification for Cyclone V  
Devices table.  
(59)  
(60)  
This specification only covers fractional PLL for low bandwidth. The fVCO for fractional value range 0.20–0.80 must be ≥ 1200 MHz.  
External memory interface clock output jitter specifications use a different measurement method, which are available in Memory  
Output Clock Jitter Specification for Cyclone V Devices table.  
Cyclone V Device Datasheet  
42  
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