Cyclone V Device Datasheet
CV-51002 | 2019.01.25
Transceiver Compliance Specification
The following table lists the physical medium attachment (PMA) specification compliance of all supported protocol for Cyclone
V GX, GT, SX, and ST devices. For more information about the protocol parameter details and compliance specifications,
contact your Intel Sales Representative.
Table 29.
Transceiver Compliance Specification for All Supported Protocol for Cyclone V GX, GT, SX, and ST Devices
Protocol
Sub-protocol
PCIe Gen1
Data Rate (Mbps)
2,500
PCIe
PCIe Gen2(50)
PCIe Cable
5,000
2,500
XAUI
XAUI 2135
3,125
Serial RapidIO® (SRIO)
SRIO 1250 SR
SRIO 1250 LR
SRIO 2500 SR
SRIO 2500 LR
SRIO 3125 SR
SRIO 3125 LR
SRIO 5000 SR
SRIO 5000 MR
SRIO 5000 LR
CPRI E6LV
1,250
1,250
2,500
2,500
3,125
3,125
5,000
5,000
5,000
Common Public Radio Interface (CPRI)
614.4
CPRI E6HV
614.4
CPRI E6LVII
614.4
continued...
(50)
For PCIe Gen2 sub-protocol, Intel recommends increasing the VCCE_GXBL and VCCL_GXBL typical value from 1.1 V to 1.2 V for Cyclone V
GT and ST FPGA systems which ensure full compliance to the PCIe Gen2 transmit jitter specification. For more information about the
maximum full duplex channels recommended in Cyclone V GT and ST devices under this condition, refer to the Transceiver Protocol
Configurations in Cyclone V Devices chapter.
Cyclone V Device Datasheet
38
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