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5CSEBA6U19I7LN 参数 Datasheet PDF下载

5CSEBA6U19I7LN图片预览
型号: 5CSEBA6U19I7LN
PDF下载: 下载PDF文件 查看货源
内容描述: [Cyclone V Device Datasheet]
分类和应用:
文件页数/大小: 93 页 / 945 K
品牌: INTEL [ INTEL ]
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Cyclone V Device Datasheet  
CV-51002 | 2019.01.25  
Symbol  
Parameter  
Condition  
Min  
Typ  
Max  
Unit  
(53)  
fVCO  
PLL voltage-controlled oscillator (VCO)  
operating range  
–C6, –C7, –I7 speed  
grades  
600  
1600  
MHz  
–C8, –A7 speed grades  
600  
40  
1300  
60  
MHz  
%
tEINDUTY  
Input clock or external feedback clock input  
duty cycle  
fOUT  
Output frequency for internal global or  
regional clock  
–C6, –C7, –I7 speed  
grades  
550(54)  
MHz  
–C8, –A7 speed grades  
460(54)  
667(54)  
MHz  
MHz  
fOUT_EXT  
Output frequency for external clock output  
–C6, –C7, –I7 speed  
grades  
–C8, –A7 speed grades  
533(54)  
55  
MHz  
%
tOUTDUTY  
Duty cycle for external clock output (when set  
to 50%)  
45  
50  
tFCOMP  
External feedback clock compensation time  
10  
ns  
tDYCONFIGCLK  
100  
MHz  
Dynamic configuration clock for mgmt_clk  
and scanclk  
tLOCK  
Time required to lock from end-of-device  
configuration or deassertion of areset  
1
1
ms  
ms  
tDLOCK  
Time required to lock dynamically (after  
switchover or reconfiguring any non-post-  
scale counters/delays)  
fCLBW  
PLL closed-loop bandwidth  
Low  
0.3  
1.5  
4
MHz  
MHz  
Medium  
High(55)  
MHz  
continued...  
(53)  
The VCO frequency reported by the Intel Quartus Prime software takes into consideration the VCO post divider value. Therefore, if the  
VCO post divider value is 2, the frequency reported can be lower than the fVCO specification.  
(54)  
(55)  
This specification is limited by the lower of the two: I/O fMAX or FOUT of the PLL.  
High bandwidth PLL settings are not supported in external feedback mode.  
Cyclone V Device Datasheet  
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