CV-51002
2015.12.04
91
Document Revision History
Date
Version
Changes
January 2015
2015.01.23
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Updated the transceiver specification for Cyclone V ST from 5 Gbps to 6.144 Gbps. Updated the note in the
following tables:
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Transceiver Power Supply Operating Conditions for Cyclone V GX, GT, SX, and ST Devices
Transceiver Specifications for Cyclone V GX, GT, SX, and ST Devices
Transceiver Compliance Specification for All Supported Protocol for Cyclone V Devices
Updated the description for VCC_AUX_SHARED to “HPS auxiliary power supply”. Added a note to state that
VCC_AUX_SHARED must be powered by the same source as VCC_AUX for Cyclone V SX C5, C6, D5, and D6
devices, and Cyclone V SE A5 and A6 devices. Updated in the following tables:
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Absolute Maximum Ratings for Cyclone V Devices
HPS Power Supply Operating Conditions for Cyclone V SE, SX, and ST Devices
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Added statement in I/O Standard Specifications: You must perform timing closure analysis to determine the
maximum achievable frequency for general purpose I/O standards.
Updated the conditions for transceiver reference clock rise time and fall time: Measure at 60 mV of
differential signal. Added a note to the conditions: REFCLK performance requires to meet transmitter REFCLK
phase noise specification.
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Updated fVCO maximum value from 1400 MHz to 1600 MHz for –C7 and –I7 speed grades in the PLL
specifications table.
Updated the description in Periphery Performance Specifications to mention that proper timing closure is
required in design.
Added the following notes in the High-Speed I/O Specifications for Cyclone V Devices table:
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The Cyclone V devices support true RSDS output standard with data rates of up to 230 Mbps using true
LVDS output buffer types on all I/O banks.
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The Cyclone V devices support true mini-LVDS output standard with data rates of up to 340 Mbps using
true LVDS output buffer types on all I/O banks.
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Updated HPS Clock Performance main_base_clk specifications from 462 MHz to 400 MHz for –C6 speed
grade.
Updated HPS PLL VCO maximum frequency to 1,600 MHz (for –C7, –I7, –A7, and –C8 speed grades) and
1,850 MHz (for –C6 speed grade).
Changed the symbol for HPS PLL input jitter divide value from NR to N.
Cyclone V Device Datasheet
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