CV-51002
2015.12.04
90
Document Revision History
Date
Version
Changes
June 2015
2015.06.12
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Updated the supported data rates for the following output standards using true LVDS output buffer types in
the High-Speed I/O Specifications for Cyclone V Devices table:
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True RSDS output standard: data rates of up to 360 Mbps
True mini-LVDS output standard: data rates of up to 400 Mbps
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Changed Queued Serial Peripheral Interface (QSPI) to Quad Serial Peripheral Interface (SPI) Flash.
Updated Th location in I2C Timing Diagram.
Updared Twp location in NAND Address Latch Timing Diagram.
Updated the maximum value for tCO from 4 ns to 2 ns in AS Timing Parameters for AS ×1 and ×4 Configu‐
rations in Cyclone V Devices table.
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Moved the following timing diagrams to the Configuration, Design Security, and Remote System Upgrades
in Cyclone V Devices chapter.
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FPP Configuration Timing Waveform When DCLK-to-DATA[] Ratio is 1
FPP Configuration Timing Waveform When DCLK-to-DATA[] Ratio is >1
AS Configuration Timing Waveform
PS Configuration Timing Waveform
March 2015
2015.03.31
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Added VCC specifications for devices with internal scrubbing feature (with SC suffix) in Recommended
Operating Conditions table.
Corrected the unit for tDH from ns to s in FPP Timing Parameters When DCLK-to-DATA[] Ratio is >1 for
Cyclone V Devices table.
Cyclone V Device Datasheet
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