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5CGTFD9E5F31C7N 参数 Datasheet PDF下载

5CGTFD9E5F31C7N图片预览
型号: 5CGTFD9E5F31C7N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 301000-Cell, CMOS, PBGA896, ROHS COMPLIANT, FBGA-896]
分类和应用: 可编程逻辑
文件页数/大小: 95 页 / 1359 K
品牌: INTEL [ INTEL ]
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CV-51002  
2015.12.04  
9
HPS Power Supply Operating Conditions  
Symbol  
Description  
Condition  
3.3 V  
3.0 V  
2.5 V  
1.8 V  
1.5 V  
1.35 V (13)  
1.2 V  
3.3 V  
3.0 V  
2.5 V  
1.8 V  
Minimum(11)  
3.135  
2.85  
Typical  
3.3  
Maximum(11)  
3.465  
3.15  
Unit  
V
3.0  
V
2.375  
1.71  
2.5  
2.625  
1.89  
V
VCCIO_HPS  
HPS I/O buffers power supply  
1.8  
V
1.425  
1.283  
1.14  
1.5  
1.575  
1.418  
1.26  
V
1.35  
1.2  
V
V
3.135  
2.85  
3.3  
3.465  
3.15  
V
3.0  
V
HPS reset and clock input pins power  
supply  
VCCRSTCLK_HPS  
2.375  
1.71  
2.5  
2.625  
1.89  
V
1.8  
V
VCCPLL_HPS  
HPS PLL analog voltage regulator power  
supply  
2.375  
2.5  
2.625  
V
VCC_AUX_  
HPS auxiliary power supply  
2.375  
2.5  
2.625  
V
(14)  
SHARED  
Related Information  
Recommended Operating Conditions on page 5  
Provides the steady-state voltage values for the FPGA portion of the device.  
(11)  
The power supply value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements.  
Refer to the PDN tool for the additional budget for the dynamic tolerance requirements.  
VCCIO_HPS 1.35 V is supported for HPS row I/O bank only.  
VCC_AUX_SHARED must be powered by the same source as VCC_AUX for Cyclone V SX C5, C6, D5, and D6 devices, and Cyclone V SE A5 and A6  
devices.  
(13)  
(14)  
Cyclone V Device Datasheet  
Send Feedback  
Altera Corporation