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5CGTFD9E5F31C7N 参数 Datasheet PDF下载

5CGTFD9E5F31C7N图片预览
型号: 5CGTFD9E5F31C7N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 301000-Cell, CMOS, PBGA896, ROHS COMPLIANT, FBGA-896]
分类和应用: 可编程逻辑
文件页数/大小: 95 页 / 1359 K
品牌: INTEL [ INTEL ]
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CV-51002  
2015.12.04  
7
Transceiver Power Supply Operating Conditions  
Symbol  
Description  
Condition  
Commercial  
Industrial  
Minimum(2)  
0
Typical  
Maximum(2)  
85  
Unit  
°C  
°C  
°C  
TJ  
Operating junction temperature  
–40  
100  
Automotive  
Standard POR  
Fast POR  
–40  
125  
200µs  
200µs  
100ms  
4ms  
(7)  
tRAMP  
Power supply ramp time  
Transceiver Power Supply Operating Conditions  
Table 4: Transceiver Power Supply Operating Conditions for Cyclone V GX, GT, SX, and ST Devices  
Symbol  
Description  
Minimum(8)  
2.375  
Typical  
2.5  
Maximum(8)  
Unit  
VCCH_GXBL  
Transceiver high voltage power (left side)  
Transmitter and receiver power (left side)  
Clock network power (left side)  
2.625  
V
V
V
(9)(10)  
VCCE_GXBL  
1.07/1.17  
1.07/1.17  
1.1/1.2  
1.1/1.2  
1.13/1.23  
1.13/1.23  
(9)(10)  
VCCL_GXBL  
(2)  
(7)  
(8)  
(9)  
The power supply value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements.  
Refer to the PDN tool for the additional budget for the dynamic tolerance requirements.  
This is also applicable to HPS power supply. For HPS power supply, refer to tRAMP specifications for standard POR when HPS_PORSEL = 0 and tRAMP  
specifications for fast POR when HPS_PORSEL = 1.  
The power supply value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements.  
Refer to the PDN tool for the additional budget for the dynamic tolerance requirements.  
Altera recommends increasing the VCCE_GXBL and VCCL_GXBL typical value from 1.1 V to 1.2 V for Cyclone V GT and ST FPGA systems which  
require full compliance to the PCIe Gen2 transmit jitter specification. For more information about the maximum full duplex channels recommended  
in Cyclone V GT and ST devices under this condition, refer to the Transceiver Protocol Configurations in Cyclone V Devices chapter.  
Altera recommends increasing the VCCE_GXBL and VCCL_GXBL typical value from 1.1 V to 1.2 V for full compliance to CPRI transmit jitter specifica‐  
tion at 4.9152 Gbps ( Cyclone V GT and ST devices) and 6.144Gbps ( Cyclone V GT and ST devices only). For more information about the  
maximum full duplex channels recommended in Cyclone V GT and ST devices for CPRI 6.144 Gbps, refer to the Transceiver Protocol Configura‐  
tions in Cyclone V Devices chapter.  
(10)  
Cyclone V Device Datasheet  
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Altera Corporation