CV-51002
2015.12.04
HPS Power Supply Operating Conditions
9
Symbol
Description
Condition
Minimum
(11)
Typical
Maximum
(11)
Unit
3.3 V
3.0 V
2.5 V
V
CCIO_HPS
HPS I/O buffers power supply
1.8 V
1.5 V
1.35 V
(13)
1.2 V
3.3 V
V
CCRSTCLK_HPS
HPS reset and clock input pins power
supply
HPS PLL analog voltage regulator power
supply
HPS auxiliary power supply
3.0 V
2.5 V
1.8 V
V
CCPLL_HPS
V
CC_AUX_
SHARED
(14)
3.135
2.85
2.375
1.71
1.425
1.283
1.14
3.135
2.85
2.375
1.71
2.375
2.375
3.3
3.0
2.5
1.8
1.5
1.35
1.2
3.3
3.0
2.5
1.8
2.5
2.5
3.465
3.15
2.625
1.89
1.575
1.418
1.26
3.465
3.15
2.625
1.89
2.625
2.625
V
V
V
V
V
V
V
V
V
V
V
V
V
—
—
Related Information
on page 5
Provides the steady-state voltage values for the FPGA portion of the device.
(11)
(13)
(14)
The power supply value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements.
Refer to the PDN tool for the additional budget for the dynamic tolerance requirements.
V
CCIO_HPS
1.35 V is supported for HPS row I/O bank only.
V
CC_AUX_SHARED
must be powered by the same source as V
CC_AUX
for Cyclone V SX C5, C6, D5, and D6 devices, and Cyclone V SE A5 and A6
devices.
Altera Corporation
Cyclone V Device Datasheet
INTEL [ INTEL CORPORATION ]
