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5CEFA5U19C8N 参数 Datasheet PDF下载

5CEFA5U19C8N图片预览
型号: 5CEFA5U19C8N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 76500-Cell, CMOS, PBGA484, ROHS COMPLIANT, UBGA-484]
分类和应用: 可编程逻辑
文件页数/大小: 95 页 / 1359 K
品牌: INTEL [ INTEL ]
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CV-51002  
2015.12.04  
11  
Bus Hold Specifications  
Bus Hold Specifications  
Table 7: Bus Hold Parameters for Cyclone V Devices  
The bus-hold trip points are based on calculated input voltages from the JEDEC standard.  
VCCIO (V)  
Parameter  
Symbol Condition  
1.2  
1.5  
1.8  
2.5  
3.0  
3.3  
Unit  
Min  
Max  
Min  
Max  
Min  
Max  
Min  
Max  
Min  
Max  
Min  
Max  
Bus-hold,  
low,  
ISUSL  
ISUSH  
IODL  
8
12  
30  
50  
70  
70  
µA  
V
IN > VIL  
(max)  
sustaining  
current  
Bus-hold,  
high,  
–8  
125  
–125  
0.9  
–12  
–30  
–50  
300  
–300  
1.7  
–70  
500  
–500  
2
–70  
500  
–500  
2
µA  
µA  
µA  
V
VIN < VIH  
(min)  
sustaining  
current  
Bus-hold,  
low,  
0 V < VIN  
< VCCIO  
175  
200  
–200  
1.07  
overdrive  
current  
Bus-hold,  
high,  
IODH  
0 V <VIN  
<VCCIO  
–175  
overdrive  
current  
Bus-hold  
trip point  
VTRIP  
0.3  
0.375 1.125  
0.68  
0.7  
0.8  
0.8  
OCT Calibration Accuracy Specifications  
If you enable on-chip termination (OCT) calibration, calibration is automatically performed at power up for I/Os connected to the calibration  
block.  
Cyclone V Device Datasheet  
Send Feedback  
Altera Corporation