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5AGXMA1D6F27C6N 参数 Datasheet PDF下载

5AGXMA1D6F27C6N图片预览
型号: 5AGXMA1D6F27C6N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 500MHz, 75000-Cell, CMOS, PBGA672, ROHS COMPLIANT, FBGA-672]
分类和应用: 可编程逻辑
文件页数/大小: 182 页 / 2239 K
品牌: INTEL [ INTEL ]
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AV-51002  
2015.12.16  
1-23  
Switching Characteristics  
Related Information  
Transceiver Specifications for Arria V GX and SX Devices on page 1-23  
Provides the specifications for transmitter, receiver, and reference clock I/O pin.  
Transceiver Specifications for Arria V GT and ST Devices on page 1-29  
Provides the specifications for transmitter, receiver, and reference clock I/O pin.  
Switching Characteristics  
This section provides performance characteristics of Arria V core and periphery blocks.  
Transceiver Performance Specifications  
Transceiver Specifications for Arria V GX and SX Devices  
Table 1-20: Reference Clock Specifications for Arria V GX and SX Devices  
Transceiver Speed Grade 4  
Transceiver Speed Grade 6  
Min Typ Max  
Symbol/Description  
Condition  
Unit  
Min  
Typ  
Max  
Supported I/O standards  
1.2 V PCML, 1.4 V PCML,1.5 V PCML, 2.5 V PCML, Differential LVPECL(23), HCSL, and LVDS  
Input frequency from  
27  
45  
710  
400  
400  
55  
27  
45  
710  
400  
400  
55  
MHz  
ps  
REFCLKinput pins  
Rise time  
Fall time  
Duty cycle  
Measure at 60 mV of  
differential signal(24)  
Measure at 60 mV of  
differential signal(24)  
ps  
%
(23)  
(24)  
Differential LVPECL signal levels must comply to the minimum and maximum peak-to-peak differential input voltage specified in this table.  
REFCLKperformance requires to meet transmitter REFCLKphase noise specification.  
Arria V GX, GT, SX, and ST Device Datasheet  
Send Feedback  
Altera Corporation  
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