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5AGXMA1D6F27C6N 参数 Datasheet PDF下载

5AGXMA1D6F27C6N图片预览
型号: 5AGXMA1D6F27C6N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 500MHz, 75000-Cell, CMOS, PBGA672, ROHS COMPLIANT, FBGA-672]
分类和应用: 可编程逻辑
文件页数/大小: 182 页 / 2239 K
品牌: INTEL [ INTEL ]
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AV-51002  
2015.12.16  
1-22  
Differential I/O Standard Specifications  
Differential I/O Standard Specifications  
Table 1-19: Differential I/O Standard Specifications for Arria V Devices  
Differential inputs are powered by VCCPD which requires 2.5 V.  
VCCIO (V)  
VID (mV)(16)  
VICM(DC) (V)  
Condition  
VOD (V)(17)  
Typ  
VOCM (V)(17)(18)  
Min Typ Max  
I/O Standard  
Min  
Typ  
Max  
Min  
Condition  
Max  
Min  
Max  
Min  
Max  
PCML  
Transmitter, receiver, and input reference clock pins of high-speed transceivers use the PCML I/O standard. For transmitter, receiver,  
and reference clock I/O pin specifications, refer to Transceiver Specifications for Arria V GX and SX Devices and Transceiver Specifica‐  
tions for Arria V GT and ST Devices tables.  
0.05  
1.05  
0.25  
0.300  
0.60  
1.00  
DMAX  
1.80  
1.55  
1.45  
1.25 Gbps  
2.5 V  
VCM  
=
2.375  
2.375  
2.5  
2.625  
100  
0.247  
0.1  
0.6  
1.125 1.25  
1.375  
LVDS(19)  
1.25 V  
DMAX  
>
1.25 Gbps  
RSDS  
2.5  
2.5  
2.625  
2.625  
100  
200  
VCM  
=
0.2  
0.6  
0.6  
0.5  
1
1.2  
1.2  
1.4  
1.4  
(HIO)(20)  
1.25 V  
Mini-LVDS 2.375  
(HIO)(21)  
600  
1.425 0.25  
1.80  
DMAX  
700 Mbps  
LVPECL(22)  
300  
DMAX  
>
1.60  
700 Mbps  
(16)  
(17)  
(18)  
(19)  
The minimum VID value is applicable over the entire common mode range, VCM  
RL range: 90 ≤ RL ≤ 110 Ω.  
.
This applies to default pre-emphasis setting only.  
For optimized LVDS receiver performance, the receiver voltage input range must be within 1.0 V to 1.6 V for data rates above 1.25 Gbps and 0 V to  
1.85 V for data rates below 1.25 Gbps.  
For optimized RSDS receiver performance, the receiver voltage input range must be within 0.25 V to 1.45 V.  
For optimized Mini-LVDS receiver performance, the receiver voltage input range must be within 0.3 V to 1.425 V.  
For optimized LVPECL receiver performance, the receiver voltage input range must be within 0.85 V to 1.75 V for data rates above 700 Mbps and  
0.45 V to 1.95 V for data rates below 700 Mbps.  
(20)  
(21)  
(22)  
Arria V GX, GT, SX, and ST Device Datasheet  
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Altera Corporation  
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