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5AGXMA1D6F27C6N 参数 Datasheet PDF下载

5AGXMA1D6F27C6N图片预览
型号: 5AGXMA1D6F27C6N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 500MHz, 75000-Cell, CMOS, PBGA672, ROHS COMPLIANT, FBGA-672]
分类和应用: 可编程逻辑
文件页数/大小: 182 页 / 2239 K
品牌: INTEL [ INTEL ]
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AV-51002  
2015.12.16  
2-80  
Document Revision History  
Date  
Version  
Changes  
July 2014  
3.8  
• Updated Table 21.  
• Updated Table 22 VOCM (DC Coupled) condition.  
• Updated the DCLK note to Figure 6, Figure 7, and Figure 9.  
• Added note to Table 5 and Table 6.  
• Added the DCLK specification to Table 50.  
• Added note to Table 51.  
• Updated the list of parameters in Table 53.  
February 2014  
December 2013  
3.7  
3.6  
Updated Table 28.  
• Updated Table 2, Table 13, Table 18, Table 19, Table 22, Table 30, Table 33, Table 37, Table 38, Table 45,  
Table 46, Table 47, Table 56, Table 49.  
• Updated “PLL Specifications”.  
August 2013  
August 2013  
3.5  
3.4  
Updated Table 28.  
• Removed Preliminary tags for Table 2, Table 4, Table 5, Table 14, Table 27, Table 28, Table 29, Table 31,  
Table 32, Table 43, Table 45, Table 46, Table 47, Table 48, Table 49, Table 50, and Table 54.  
• Updated Table 2 and Table 28.  
June 2013  
May 2013  
3.3  
3.2  
Updated Table 23, Table 28, Table 51, and Table 55.  
• Added Table 23.  
• Updated Table 5, Table 22, Table 26, and Table 57.  
• Updated Figure 6, Figure 7, Figure 8, and Figure 9.  
March 2013  
3.1  
3.0  
• Updated Table 2, Table 6, Table 7, Table 8, Table 19, Table 22, Table 26, Table 29, Table 52.  
• Updated “Maximum Allowed Overshoot and Undershoot Voltage”.  
December 2012  
Initial release.  
Arria V GZ Device Datasheet  
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