AV-51002
2015.12.16
2-78
Glossary
Term
Definition
TCCS (channel-to-
channel-skew)
The timing difference between the fastest and slowest output edges, including tCO variation and clock skew, across
channels driven by the same PLL. The clock is included in the TCCS measurement (refer to the Timing Diagram figure
under SW in this table).
tDUTY
High-speed I/O block—Duty cycle on the high-speed transmitter output clock.
Signal high-to-low transition time (80-20%)
tFALL
tINCCJ
Cycle-to-cycle jitter tolerance on the PLL clock input.
Period jitter on the general purpose I/O driven by a PLL.
Period jitter on the dedicated clock output driven by a PLL.
Signal low-to-high transition time (20-80%)
tOUTPJ_IO
tOUTPJ_DC
tRISE
Timing Unit Interval The timing budget allowed for skew, propagation delays, and the data sampling window.
(TUI)
VCM(DC)
VICM
(TUI = 1/(receiver input clock frequency multiplication factor) = tC/w)
DC common mode input voltage.
Input common mode voltage—The common mode of the differential signal at the receiver.
VID
Input differential voltage swing—The difference in voltage between the positive and complementary conductors of a
differential transmission at the receiver.
VDIF(AC)
VDIF(DC)
VIH
AC differential input voltage—Minimum AC input differential voltage required for switching.
DC differential input voltage— Minimum DC input differential voltage required for switching.
Voltage input high—The minimum positive voltage applied to the input which is accepted by the device as a logic high.
High-level AC input voltage
VIH(AC)
VIH(DC)
VIL
High-level DC input voltage
Voltage input low—The maximum positive voltage applied to the input which is accepted by the device as a logic low.
Low-level AC input voltage
VIL(AC)
VIL(DC)
VOCM
Low-level DC input voltage
Output common mode voltage—The common mode of the differential signal at the transmitter.
Arria V GZ Device Datasheet
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