AV-51002
2015.12.16
2-77
Glossary
Term
Definition
SW (sampling
window)
Timing Diagram—the period of time during which the data must be valid in order to capture it correctly. The setup and
hold times determine the ideal strobe position within the sampling window, as shown:
Bit Time
Sampling Window
(SW)
RSKM
RSKM
0.5 x TCCS
0.5 x TCCS
Single-ended voltage The JEDEC standard for SSTL and HSTL I/O defines both the AC and DC input signal values. The AC values indicate the
referenced I/O
standard
voltage levels at which the receiver must meet its timing specifications. The DC values indicate the voltage levels at which
the final logic state of the receiver is unambiguously defined. After the receiver input has crossed the AC value, the receiver
changes to the new logic state.
The new logic state is then maintained as long as the input stays beyond the DC threshold. This approach is intended to
provide predictable receiver timing in the presence of input waveform ringing:
Single-Ended Voltage Referenced I/O Standard
V CCIO
VOH
VIH AC
(
)
VIH(DC )
V REF
V IL(DC )
V IL(AC
)
VOL
VSS
tC
High-speed receiver and transmitter input and output clock period.
Arria V GZ Device Datasheet
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