AV-51002
2015.12.16
2-76
Glossary
Term
Definition
JTAG Timing Specifi‐ JTAG Timing Specifications:
cations
TMS
TDI
t
JCP
t
t
t
JPH
t
JCH
JCL
JPSU
TCK
t
t
t
JPCO
JPZX
JPXZ
TDO
PLL Specifications
Diagram of PLL Specifications
CLKOUT Pins
fOUT_EXT
Switchover
fIN
4
CLK
fINPFD
N
GCLK
RCLK
Counters
C 0..C 17
fVCO
VCO
fOUT
PFD
CP
LF
Core Clock
Delta Sigma
Modulator
Key
External Feedback
Reconfigurable in User Mode
Note:
1. Core Clock can only be fed by dedicated clock input pins or PLL outputs.
RL
Receiver differential input discrete resistor (external to the Arria V GZ device).
Arria V GZ Device Datasheet
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Altera Corporation
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