AV-51002
2017.02.10
2-67
Passive Serial Configuration Timing
Passive Serial Configuration Timing
Figure 2-10: PS Configuration Timing Waveform
Timing waveform for a passive serial (PS) configuration when using a MAX II device, MAX V device, or microprocessor as an external host.
t
CF2ST1
t
CFG
t
CF2CK
nCONFIG
nSTATUS (2)
t
STATUS
(6)
t
CF2ST0
t
CLK
CONF_DONE (3)
t
CH
t
CL
t
CF2CD
t
ST2CK
(4)
(5)
DCLK
t
DH
DATA0
Bit 2
Bit 0 Bit 1
Bit 3
Bit (n-1)
t
DSU
User I/O
User Mode
High-Z
INIT_DONE (7)
t
CD2UM
Notes:
1. The beginning of this waveform shows the device in user mode. In user mode, nCONFIG, nSTATUS,
and CONF_DONE are at logic high levels. When nCONFIG is pulled low, a reconfiguration cycle begins.
2. After power-up, the Arria V GZ device holds nSTATUS low for the time of the POR delay.
3. After power-up, before and during configuration, CONF_DONE is low.
4. Do not leave DCLK floating after configuration. DCLK is ignored after configuration is complete.
It can toggle high or low if required.
5. DATA0 is available as a user I/O pin after configuration. The state of this pin depends on the
dual-purpose pin settings in the Device and Pins Option.
6. To ensure a successful configuration, send the entire configuration data to the Arria V GZ device.
CONF_DONE is released high after the Arria V GZ device receives all the configuration data
successfully. After CONF_DONE goes high, send two additional falling edges on DCLK to begin
initialization and enter user mode.
7. After the option bit to enable the INIT_DONE pin is configured into the device, the INIT_DONE goes low.
Arria V GZ Device Datasheet
Send Feedback
Altera Corporation
INTEL [ INTEL ]
