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5AGXFA5H4F35C5N 参数 Datasheet PDF下载

5AGXFA5H4F35C5N图片预览
型号: 5AGXFA5H4F35C5N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 622MHz, 190000-Cell, CMOS, PBGA1152, ROHS COMPLIANT, FBGA-1152]
分类和应用: 时钟可编程逻辑
文件页数/大小: 184 页 / 1761 K
品牌: INTEL [ INTEL ]
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AV-51002  
2017.02.10  
2-65  
Active Serial Configuration Timing  
Active Serial Configuration Timing  
Figure 2-9: AS Configuration Timing  
Timing waveform for the active serial (AS) x1 mode and AS x4 mode configuration timing.  
t
CF2ST1  
nCONFIG  
nSTATUS  
CONF_DONE  
nCSO  
DCLK  
t
CO  
t
DH  
Read Address  
AS_DATA0/ASDO  
AS_DATA1 (1)  
INIT_DONE (3)  
t
SU  
bit (n - 2) bit (n - 1)  
bit 1  
bit 0  
t
(2)  
CD2UM  
User I/O  
User Mode  
Notes:  
1.If you are using AS ×4 mode, this signal represents the AS_DATA[3..0] and EPCQ sends in 4-bits of data for each DCLKcycle.  
2.The initialization clock can be from internal oscillator or CLKUSR pi.n  
3.After the option bit to enable the INIT_DONE pin isconfigured into the d evice, the INIT_DONE oges low.  
Table 2-58: AS Timing Parameters for AS x1 and AS x4 Configurations in Arria V GZ Devices  
e minimum and maximum numbers apply only if you choose the internal oscillator as the clock source for initializing the device.  
tCF2CD, tCF2ST0, tCFG, tSTATUS, and tCF2ST1 timing parameters are identical to the timing parameters for PS mode listed in the "PS Timing Parameters  
for Arria V GZ Devices" table.  
Arria V GZ Device Datasheet  
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Altera Corporation