Switching Characteristics
Page 47
I2C Timing Characteristics
Table 49 lists the I2C timing characteristics for Arria V devices.
Table 49. I2C Timing Requirements for Arria V Devices
Standard Mode
Fast Mode
Symbol
Description
Unit
Min
—
4.7
4
Max
10
Min
Max
2.5
—
Tclk
Tclkhigh
Tclklow
Serial clock (SCL) clock period
SCL high time
—
0.6
1.3
µs
µs
µs
—
SCL low time
—
—
Setup time for serial data line (SDA) data to
SCL
Ts
0.25
—
0.1
—
µs
Th
Hold time for SCL to SDA data
0
—
4.7
4
3.45
0.2
—
0
0.9
0.2
—
µs
µs
µs
µs
µs
Td
SCL to SDA output data delay
—
Tsu_start
Thd_start
Tsu_stop
Setup time for a repeated start condition
Hold time for a repeated start condition
Setup time for a stop condition
0.6
0.6
0.6
—
—
4
—
—
Figure 15 shows the timing diagram for I2C timing characteristics.
Figure 15. I2C Timing Diagram
I2C_SCL
Td
Ts
Tsu_stop
Tsu_start Thd_start
Th
Data In
Data Out
I2C_SDA
NAND Timing Characteristics
Table 50 lists the NAND timing characteristics for Arria V devices.
The NAND controller supports Open NAND FLASH Interface (ONFI) 1.0 Mode 5
timing as well as legacy NAND devices. The following table lists the requirements for
ONFI 1.0 mode 5 timing. The HPS NAND controller can meet this timing by
programming the C4output of the main HPS PLL and timing registers provided in the
NAND controller.
Table 50. NAND ONFI 1.0 Timing Requirements for Arria V Devices (Part 1 of 2)
Symbol
(1)
Description
Write enable pulse width
Min
10
7
Max
—
—
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
Twp
Twh
(1)
Write enable hold time
(1)
Trp
Read Enable pulse width
10
7
(1)
(1)
Treh
Read enable hold time
Tclesu
Command latch enable to write enable setup time
Command latch enable to write enable hold time
Chip enable to write enable setup time
10
5
(1)
Tcleh
(1)
Tcesu
15
December 2013 Altera Corporation
Arria V GX, GT, SX, and ST Device Datasheet
INTEL [ INTEL ]
