Page 46
Switching Characteristics
Table 47 lists the RGMII RX timing characteristics for Arria V devices.
Table 47. RGMII RX Timing Requirements for Arria V Devices
Symbol
Description
RX_CLK clock period
Min
—
—
—
1
Typ
Unit
ns
Tclk (1000Base-T)
8
T
clk (100Base-T)
clk (10Base-T)
Tsu
RX_CLK clock period
RX_CLK clock period
RX_D/RX_CTL setup time
40
ns
T
400
—
ns
ns
Figure 13 shows the timing diagram for RGMII RX timing characteristics.
Figure 13. RGMII RX Timing Diagram
RX_CLK
Tsu
RX_D[3:0]
RX_CTL
Table 48 lists the management data input/output (MDIO) timing characteristics for
Arria V devices.
Table 48. MDIO Timing Requirements for Arria V Devices
Symbol Description
Min
—
10
10
0
Typ
400
—
Unit
ns
Tclk
Td
Ts
MDC clock period
MDC to MDIO output data delay
Setup time for MDIO data
Hold time for MDIO data
ns
—
ns
Th
—
ns
Figure 14 shows the timing diagram for MDIO timing characteristics.
Figure 14. MDIO Timing Diagram
MDC
Td
MDIO_OUT
MDIO_IN
Th
Tsu
Arria V GX, GT, SX, and ST Device Datasheet
December 2013 Altera Corporation
INTEL [ INTEL ]
