Land Listing and Signal Descriptions
Table 4-3. Signal Description (Sheet 6 of 8)
Name
Type
Description
As an output, PROCHOT# (Processor Hot) will go active when the processor
temperature monitoring sensor detects that the processor has reached its
maximum safe operating temperature. This indicates that the processor
Thermal Control Circuit (TCC) has been activated, if enabled. As an input,
assertion of PROCHOT# by the system will activate the TCC, if enabled. The
TCC will remain active until the system de-asserts PROCHOT#. See
Section 5.2.4 for more details.
Input/
Output
PROCHOT#
PWRGOOD (Power Good) is a processor input. The processor requires this
signal to be a clean indication that the clocks and power supplies are stable and
within their specifications. ‘Clean’ implies that the signal will remain low
(capable of sinking leakage current), without glitches, from the time that the
power supplies are turned on until they come within specification. The signal
must then transition monotonically to a high state. PWRGOOD can be driven
inactive at any time, but clocks and power must again be stable before a
subsequent rising edge of PWRGOOD. The PWRGOOD signal must be
supplied to the processor; it is used to protect internal circuits against voltage
sequencing issues. It should be driven high throughout boundary scan
operation.
PWRGOOD
Input
REQ[4:0]# (Request Command) must connect the appropriate pins/lands of all
processor FSB agents. They are asserted by the current bus owner to define
the currently active transaction type. These signals are source synchronous to
ADSTB0#. Refer to the AP[1:0]# signal description for a details on parity
checking of these signals.
Input/
Output
REQ[4:0]#
Asserting the RESET# signal resets the processor to a known state and
invalidates its internal caches without writing back any of their contents. For a
power-on Reset, RESET# must stay active for at least one millisecond after
V
CC and BCLK have reached their proper specifications. On observing active
RESET#, all FSB agents will de-assert their outputs within two clocks. RESET#
must not be kept asserted for more than 10 ms while PWRGOOD is asserted.
RESET#
Input
A number of bus signals are sampled at the active-to-inactive transition of
RESET# for power-on configuration. These configuration options are described
in the Section 6.1.
This signal does not have on-die termination and must be terminated on the
system board.
RS[2:0]# (Response Status) are driven by the response agent (the agent
responsible for completion of the current transaction), and must connect the
appropriate pins/lands of all processor FSB agents.
RS[2:0]#
RSP#
Input
Input
RSP# (Response Parity) is driven by the response agent (the agent responsible
for completion of the current transaction) during assertion of RS[2:0]#, the
signals for which RSP# provides parity protection. It must connect to the
appropriate pins/lands of all processor FSB agents.
A correct parity signal is high if an even number of covered signals are low and
low if an odd number of covered signals are low. While RS[2:0]# = 000, RSP# is
also high, since this indicates it is not being driven by any agent guaranteeing
correct parity.
SKTOCC# (Socket Occupied) will be pulled to ground by the processor. System
board designers may use this signal to determine if the processor is present.
SKTOCC#
SMI#
Output
Input
SMI# (System Management Interrupt) is asserted asynchronously by system
logic. On accepting a System Management Interrupt, the processor saves the
current state and enter System Management Mode (SMM). An SMI
Acknowledge transaction is issued, and the processor begins program
execution from the SMM handler.
If SMI# is asserted during the de-assertion of RESET#, the processor will tri-
state its outputs.
Datasheet
71
INTEL [ INTEL ]
