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550 参数 Datasheet PDF下载

550图片预览
型号: 550
PDF下载: 下载PDF文件 查看货源
内容描述: 奔腾4处理器,支持超线程技术 [Pentium 4 Processors Supporting Hyper-Threading Technology]
分类和应用:
文件页数/大小: 96 页 / 1585 K
品牌: INTEL [ INTEL ]
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Land Listing and Signal Descriptions  
Table 4-3. Signal Description (Sheet 7 of 8)  
Name  
Type  
Description  
STPCLK# (Stop Clock), when asserted, causes the processor to enter a low  
power Stop-Grant state. The processor issues a Stop-Grant Acknowledge  
transaction, and stops providing internal clock signals to all processor core units  
except the FSB and APIC units. The processor continues to snoop bus  
transactions and service interrupts while in Stop-Grant state. When STPCLK# is  
de-asserted, the processor restarts its internal clock to all units and resumes  
execution. The assertion of STPCLK# has no effect on the bus clock; STPCLK#  
is an asynchronous input.  
STPCLK#  
Input  
TCK (Test Clock) provides the clock input for the processor Test Bus (also  
known as the Test Access Port).  
TCK  
TDI  
Input  
Input  
TDI (Test Data In) transfers serial test data into the processor. TDI provides the  
serial input needed for JTAG specification support.  
TDO (Test Data Out) transfers serial test data out of the processor. TDO  
provides the serial output needed for JTAG specification support.  
TDO  
Output  
TESTHI[13:0] must be connected to the processor’s appropriate power source  
(refer to VTT_OUT_LEFT and VTT_OUT_RIGHT signal description) through a  
resistor for proper processor operation. See Section 2.5 for more details.  
TESTHI[13:0]  
Input  
THERMDA  
THERMDC  
Other Thermal Diode Anode. See Section 5.2.7.  
Other Thermal Diode Cathode. See Section 5.2.7.  
In the event of a catastrophic cooling failure, the processor will automatically  
shut down when the silicon has reached a temperature approximately 20 °C  
above the maximum TC. Assertion of THERMTRIP# (Thermal Trip) indicates the  
processor junction temperature has reached a level beyond where permanent  
silicon damage may occur. Upon assertion of THERMTRIP#, the processor will  
shut off its internal clocks (thus, halting program execution) in an attempt to  
reduce the processor junction temperature. To protect the processor, its core  
Output voltage (VCC) must be removed following the assertion of THERMTRIP#.  
Driving of the THERMTRIP# signal is enabled within 10 µs of the assertion of  
PWRGOOD and is disabled on de-assertion of PWRGOOD. Once activated,  
THERMTRIP# remains latched until PWRGOOD is de-asserted. While the de-  
assertion of the PWRGOOD signal will de-assert THERMTRIP#, if the  
processor’s junction temperature remains at or above the trip level,  
THERMTRIP# will again be asserted within 10 µs of the assertion of  
PWRGOOD.  
THERMTRIP#  
TMS (Test Mode Select) is a JTAG specification support signal used by debug  
TMS  
Input  
tools.  
TRDY# (Target Ready) is asserted by the target to indicate that it is ready to  
TRDY#  
Input  
receive a write or implicit writeback data transfer. TRDY# must connect the  
appropriate pins/lands of all FSB agents.  
TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# must be  
driven low during power on Reset.  
TRST#  
VCC  
Input  
Input  
VCC are the power pins for the processor. The voltage supplied to these pins is  
determined by the VID[5:0] pins.  
VCCA  
Input  
Input  
VCCA provides isolated power for the internal processor core PLLs.  
VCCIOPLL provides isolated power for internal processor FSB PLLs.  
VCC_SENSE is an isolated low impedance connection to processor core power  
VCCIOPLL  
VCC_SENSE  
Output (VCC). It can be used to sense or measure voltage near the silicon with little  
noise.  
This land is provided as a voltage regulator feedback sense point for VCC. It is  
connected internally in the processor package to the sense point land U27 as  
described in the Voltage Regulator-Down (VRD) 10.1 Design Guide for Desktop  
VCC_MB_  
REGULATION  
Output  
Socket 775.  
72  
Datasheet  
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