Features
needs to account for a variable number of processors asserting the Stop Grant SBC on
the bus before allowing the processor to be transitioned into one of the lower processor
power states. Refer to the applicable chipset specification for more information.
7.2.1
Normal State
This is the normal operating state for the processor.
7.2.2
HALT or Enhanced Powerdown States
The Enhanced HALT power down state is enabled by default in the Dual-Core Intel Xeon
Processor 5000 series. The Enhanced HALT power down state must remain enabled
via the BIOS. The Enhanced HALT state requires support for dynamic VID transitions in
the platform.
7.2.2.1
HALT Powerdown State
HALT is a low power state entered when all logical processors have executed the HALT
or MWAIT instruction. When one of the logical processors executes the HALT or MWAIT
instruction, that logical processor is halted; however, the other processor continues
normal operation. The processor will transition to the Normal state upon the occurrence
of SMI#, BINIT#, INIT#, LINT[1:0] (NMI, INTR), or an interrupt delivered over the
front side bus. RESET# will cause the processor to immediately initialize itself.
The return from a System Management Interrupt (SMI) handler can be to either
Normal Mode or the HALT Power Down state. Refer to the
IA-32 Intel
®
Architecture
Software Developer's Manual, Volume III: System Programming Guide
for more
information.
The system can generate a STPCLK# while the processor is in the HALT Power Down
state. When the system deasserts the STPCLK#, the processor will return execution to
the HALT state.
While in HALT Power Down state, the processor will process front side bus snoops and
interrupts.
7.2.2.2
Enhanced HALT Powerdown State
Enhanced HALT state is a low power state entered when all logical processors have
executed the HALT or MWAIT instructions. When one of the logical processors executes
the HALT instruction, that logical processor is halted; however, the other processor
continues normal operation. The Enhanced HALT state is generally a lower power state
than the Stop Grant state.
The processor will automatically transition to a lower core frequency and voltage
operating point before entering the Enhanced HALT state. Note that the processor FSB
frequency is not altered; only the internal core frequency is changed. When entering
the low power state, the processor will first switch to the lower bus ratio and then
transition to the lower VID.
While in the Enhanced HALT state, the processor will process bus snoops.
The processor exits the Enhanced HALT state when a break event occurs. When the
processor exits the Enhanced HALT state, it will first transition the VID to the original
value and then change the bus ratio back to the original value.
84
Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
INTEL [ INTEL CORPORATION ]
