Processor Configuration Registers
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/0/0/GFXVTBAR
34–37h
00000000h
RO, ROS-V, RW1CS
32 bits
Size:
BIOS Optimal Default
00000h
Reset
Value
RST/
PWR
Bit
Access
Description
Advanced Fault Overflow (AFO)
Hardware sets this field to indicate advanced fault log overflow
condition. At this time, a fault event is generated based on the
programming of the Fault Event Control register.
2
RO
0b
Uncore
Software writing 1 to this field clears it.
Hardware implementations not supporting advanced fault
logging implement this bit as RsvdZ.
Primary Pending Fault (PPF)
This field indicates if there are one or more pending faults
logged in the fault recording registers. Hardware computes this
field as the logical OR of Fault (F) fields across all the fault
recording registers of this remapping hardware unit.
1
0
ROS-V
0b
0b
Powergood
Powergood
0 =No pending faults in any of the fault recording registers
1 = One or more fault recording registers has pending faults.
The FRI field is updated by hardware whenever the PPF
field is set by hardware. Also, depending on the
programming of Fault Event Control register, a fault event
is generated when hardware sets this field.
Primary Fault Overflow (PFO)
Hardware sets this field to indicate overflow of fault recording
registers. Software writing 1 clears this field. When this field is
set, hardware does not record any new faults until software
clears this field.
RW1CS
276
Datasheet, Volume 2
INTEL [ INTEL ]
