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326769-002 参数 Datasheet PDF下载

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型号: 326769-002
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内容描述: 移动第三代英特尔®科雷亚?? ¢处理器家族 [Mobile 3rd Generation Intel® Core™ Processor Family]
分类和应用:
文件页数/大小: 342 页 / 2513 K
品牌: INTEL [ INTEL ]
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Processor Configuration Registers  
2.18.8  
FSTS_REG—Fault Status Register  
This register indicates the various error status.  
B/D/F/Type:  
Address Offset:  
Reset Value:  
Access:  
0/0/0/GFXVTBAR  
34–37h  
00000000h  
RO, ROS-V, RW1CS  
32 bits  
Size:  
BIOS Optimal Default  
00000h  
Reset  
Value  
RST/  
PWR  
Bit  
Access  
Description  
31:16  
RO  
0h  
Reserved (RSVD)  
Fault Record Index (FRI)  
This field is valid only when the PPF field is set.  
The FRI field indicates the index (from base) of the fault  
recording register to which the first pending fault was recorded  
when the PPF field was set by hardware.  
15:8  
ROS-V  
00h  
Powergood  
The value read from this field is undefined when the PPF field is  
clear.  
7
6
RO  
RO  
0h  
0b  
Reserved (RSVD)  
Invalidation Time-out Error (ITE)  
Hardware detected a Device-IOTLB invalidation completion  
time-out. At this time, a fault event may be generated based  
on the programming of the Fault Event Control register.  
Hardware implementations not supporting device Device-  
IOTLBs implement this bit as RsvdZ.  
Uncore  
Uncore  
Invalidation Completion Error (ICE)  
Hardware received an unexpected or invalid Device-IOTLB  
invalidation completion. This could be due to either an invalid  
ITag or invalid source-id in an invalidation completion  
response. At this time, a fault event may be generated based  
on the programming of the Fault Event Control register.  
Hardware implementations not supporting Device-IOTLBs  
implement this bit as RsvdZ.  
5
4
3
RO  
RW1CS  
RO  
0b  
0b  
0b  
Invalidation Queue Error (IQE)  
Hardware detected an error associated with the invalidation  
queue. This could be due to either a hardware error while  
fetching a descriptor from the invalidation queue, or hardware  
Powergood detecting an erroneous or invalid descriptor in the invalidation  
queue. At this time, a fault event may be generated based on  
the programming of the Fault Event Control register.  
Hardware implementations not supporting queued invalidations  
implement this bit as RsvdZ.  
Advanced Pending Fault (APF)  
When this field is clear, hardware sets this field when the first  
fault record (at index 0) is written to a fault log. At this time, a  
fault event is generated based on the programming of the Fault  
Event Control register.  
Uncore  
Software writing 1 to this field clears it. Hardware  
implementations not supporting advanced fault logging  
implement this bit as RsvdZ.  
Datasheet, Volume 2  
275